From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 949C8A00C4; Thu, 29 Sep 2022 09:44:14 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3B70E40E5A; Thu, 29 Sep 2022 09:44:14 +0200 (CEST) Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) by mails.dpdk.org (Postfix) with ESMTP id 5927440694 for ; Thu, 29 Sep 2022 09:44:13 +0200 (CEST) Received: by mail-wr1-f42.google.com with SMTP id cc5so803291wrb.6 for ; Thu, 29 Sep 2022 00:44:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind.com; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date; bh=YY/5HICdoR9MhLvl/ZtF6EYQJPVClYySsE4obwLANuw=; b=JWgof00Q7cP74FlB6nkVpRyaQwsyQrJDUNP96B4NU0T2VGw/4Wzw2QcpBb5ol/+Kiu schwDvZ8IyTZ3D5bWb54ul23M2EIQkVHNxvhfEU9AiV2BhNH1zl/w1LCq3R3Zcffhjkb UNWnM2e+nShb4yqSCvOQg6OnQTisTExxHw0LDVDEF+02EJAsZqVd9H1J7s/QCEx/uexz wM9MY/RkyVE1QjB8QumrQEJISYzYs2p0HXhuqYutDtKmJXZ4FTaNghJoTqUMpCSrHKr8 Rsb0wTyxdBt+ti3b34//042MHVl+zF6l0Or+yYEoTGeKXAsu4PiZZKQLWFQlspbV4qni aHNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date; bh=YY/5HICdoR9MhLvl/ZtF6EYQJPVClYySsE4obwLANuw=; b=ubSS381lnFEDRjxA174tC0998IFj7OQ5Yjx2gA2wC17NfdOtk/5UZec+aVJ/B9YC7Z Uasj+5+tCZIx6V9N88h66S8udAze+MMTYDgOQPPleyWtrNiOueZPovmY9A0Tgf5DvCsK mMSoBophRwY5Ce7Smr0D1Cb0HcK2r6yFfbhZuf1xsGpATQ9ANxkBOEHce6R1YPr7wZ4n ueijqn1UjgSkeX0IsCefnq22Jy6KElJBr9aJYnQDHcSQmznZvkt3Sk3g1u8QhLTcqToP 8ZHWpwY6RTNecdcPWy91Nrq4TU65+slsYvglY5x68km4HShK7bQXw8yXJWbz0lVmO2IQ ZWLA== X-Gm-Message-State: ACrzQf0mO3P+FVj/0j2lmdd1v4t9dwS/KHqItup3+8msgX3kUiWGC+nk 1HKnmTWC7dz5K5VTWbYzSoZguQ== X-Google-Smtp-Source: AMsMyM7AOP/TNjvjpDGNWQl141Xs/79eP9GrO601ybRAR2+0N+Ib8iMDyYR/O0LiW3x9tPQfbohUXA== X-Received: by 2002:a5d:47a9:0:b0:22a:4746:cfa7 with SMTP id 9-20020a5d47a9000000b0022a4746cfa7mr1114110wrb.368.1664437453019; Thu, 29 Sep 2022 00:44:13 -0700 (PDT) Received: from 6wind.com ([2a01:e0a:5ac:6460:c065:401d:87eb:9b25]) by smtp.gmail.com with ESMTPSA id w1-20020a5d5441000000b0022cc0a2cbecsm5623394wrv.15.2022.09.29.00.44.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Sep 2022 00:44:12 -0700 (PDT) Date: Thu, 29 Sep 2022 09:44:11 +0200 From: Olivier Matz To: Shijith Thotton Cc: "dev@dpdk.org" , Pavan Nikhilesh Bhagavatula , "Honnappa.Nagarahalli@arm.com" , "bruce.richardson@intel.com" , Jerin Jacob Kollanukkaran , "mb@smartsharesystems.com" , "stephen@networkplumber.org" , "thomas@monjalon.net" , "david.marchand@redhat.com" , Ruifeng Wang , Jan Viktorin , Nithin Kumar Dabilpuram , Kiran Kumar Kokkilagadda , Sunil Kumar Kori , Satha Koteswara Rao Kottidi , Ankur Dwivedi , Anoob Joseph , Tejasree Kondoj , Radha Chintakuntla , Veerasenareddy Burru , Ashwin Sekhar T K , Jakub Palider , Tomasz Duszynski Subject: Re: [EXT] Re: [PATCH v3 4/5] drivers: mark Marvell cnxk PMDs work with IOVA as VA Message-ID: References: <20220907134340.3629224-1-sthotton@marvell.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Thu, Sep 29, 2022 at 06:19:32AM +0000, Shijith Thotton wrote: > >> Enabled the flag pmd_iova_as_va in cnxk driver build files as they work > >> with IOVA as VA. Updated cn9k and cn10k soc build configurations to > >> enable the IOVA as VA build by default. > >> > >> Signed-off-by: Shijith Thotton > >> --- > >> config/arm/meson.build | 8 +++- > >> drivers/common/cnxk/meson.build | 1 + > >> drivers/crypto/cnxk/cn10k_ipsec_la_ops.h | 4 +- > >> drivers/crypto/cnxk/cn9k_ipsec_la_ops.h | 2 +- > >> drivers/crypto/cnxk/meson.build | 2 + > >> drivers/dma/cnxk/meson.build | 1 + > >> drivers/event/cnxk/meson.build | 1 + > >> drivers/mempool/cnxk/meson.build | 1 + > >> drivers/net/cnxk/cn10k_tx.h | 55 +++++++----------------- > >> drivers/net/cnxk/cn9k_tx.h | 55 +++++++----------------- > >> drivers/net/cnxk/cnxk_ethdev.h | 1 - > >> drivers/net/cnxk/meson.build | 1 + > >> drivers/raw/cnxk_bphy/meson.build | 1 + > >> drivers/raw/cnxk_gpio/meson.build | 1 + > >> 14 files changed, 50 insertions(+), 84 deletions(-) > >> > >> diff --git a/config/arm/meson.build b/config/arm/meson.build > >> index 9f1636e0d5..4e95e8b388 100644 > >> --- a/config/arm/meson.build > >> +++ b/config/arm/meson.build > >> @@ -294,7 +294,8 @@ soc_cn10k = { > >> 'flags': [ > >> ['RTE_MAX_LCORE', 24], > >> ['RTE_MAX_NUMA_NODES', 1], > >> - ['RTE_MEMPOOL_ALIGN', 128] > >> + ['RTE_MEMPOOL_ALIGN', 128], > >> + ['RTE_IOVA_AS_VA', 1] > >> ], > >> 'part_number': '0xd49', > >> 'extra_march_features': ['crypto'], > >> @@ -370,7 +371,10 @@ soc_cn9k = { > >> 'description': 'Marvell OCTEON 9', > >> 'implementer': '0x43', > >> 'part_number': '0xb2', > >> - 'numa': false > >> + 'numa': false, > >> + 'flags': [ > >> + ['RTE_IOVA_AS_VA', 1] > >> + ] > >> } > > > >I think this could go in a separate patch: "disable IOVA as PA for octeontx2/3" > > > >The reason is that this patch clearly breaks the API (m->buf_iova field > >becomes invalid) and the ABI (mbuf fields are moved) for these > >architectures. This ABI breakage has to be advertised in the release > >note. In fact, it should have been advertised before, but I suppose it > >does not impact general purpose arm distributions, so I guess it is ok. > > > >One other thing to highlight: enabling RTE_IOVA_AS_VA means that it > >disable all drivers that do not have the pmd_iova_as_va flag. Are there > >use-cases where drivers other than cnxk are used? For instance, is there > >a PCI bus which is likely to be used by a driver/* ? > > > > All always enable drivers are enabled in this mode, which include > bus/pci, bus/vdev and mempool/ring. I was thinking about use cases where a pci PMD (NIC, crypto, ...) is used in addition to the SOC drivers. These PMD won't compile when IOVA as PA is disabled, and the use case will be broken. This is probably a corner case (people at Marvell will know better than me), I just wanted to highlight it. Should we document it? Thanks, Olivier