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Mon, 2 Dec 2024 14:09:44 +0000 Date: Mon, 2 Dec 2024 14:09:35 +0000 From: Bruce Richardson To: "Medvedkin, Vladimir" CC: , Anatoly Burakov , "Wathsala Vithanage" , Konstantin Ananyev Subject: Re: [PATCH v1 09/21] net/ixgbe: use common Tx queue structure Message-ID: References: <20241122125418.2857301-1-bruce.richardson@intel.com> <20241202112444.1517416-1-bruce.richardson@intel.com> <20241202112444.1517416-10-bruce.richardson@intel.com> <69c37ea1-5171-42c1-a5bf-c5572fc2d037@intel.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <69c37ea1-5171-42c1-a5bf-c5572fc2d037@intel.com> X-ClientProxiedBy: ZR0P278CA0088.CHEP278.PROD.OUTLOOK.COM (2603:10a6:910:22::21) To DS0PR11MB7309.namprd11.prod.outlook.com (2603:10b6:8:13e::17) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR11MB7309:EE_|DM6PR11MB4706:EE_ X-MS-Office365-Filtering-Correlation-Id: 0d84ba06-40ae-46b8-b28c-08dd12daf8dd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|366016; 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> volatile struct iavf_tx_desc *iavf_tx_ring; > volatile struct ice_tx_desc *ice_tx_ring; > + volatile union ixgbe_adv_tx_desc *ixgbe_tx_ring; > }; > volatile uint8_t *qtx_tail; /* register address of tail */ > - struct ci_tx_entry *sw_ring; /* virtual address of SW ring */ > + union { > + struct ci_tx_entry *sw_ring; /* virtual address of SW ring */ > + struct ci_tx_entry_vec *sw_ring_vec; > + }; > rte_iova_t tx_ring_dma; /* TX ring DMA address */ > uint16_t nb_tx_desc; /* number of TX descriptors */ > uint16_t tx_tail; /* current value of tail register */ > @@ -87,6 +91,14 @@ struct ci_tx_queue { > uint8_t tc; > bool use_ctx; /* with ctx info, each pkt needs two desc > riptors */ > }; > + struct { /* ixgbe specific values */ > + const struct ixgbe_txq_ops *ops; > + struct ixgbe_advctx_info *ctx_cache; > > 'struct ixgbe_advctx_info ctx_cache[IXGBE_CTX_NUM];' takes only 80 > bytes of memory, so using a pointer saves 72 bytes. Since the final > version of the 'struct ci_tx_queue' without driver specific fields > takes 96 bytes, embedding 'ixgbe_advctx_info ctx_cache[2]' array will > take one more cache line, which is hot a huge deal in my opinion. > Maybe not, though another way to look at it is that it is that those two context entries are nearly as big as the rest of the struct! > Or consider another (possibly better) approach, where for non IXGBE > 'struct ci_tx_queue' will remain the same size, but only for IXGBE an > extra 80 bytes will be alllocated: > > struct { /* ixgbe specific values */ > > const struct ixgbe_txq_ops *ops; > > uint32_t ctx_curr; > > uint8_t pthresh; /**< Prefetch threshold > register. */ > > uint8_t hthresh; /**< Host threshold > register. */ > > uint8_t wthresh; /**< Write-back threshold > reg. */ > > uint8_t using_ipsec; /**< indicates that IPsec > TX feature is in use */ > struct ixgbe_advctx_info ctx_cache[0]; > > }; > > + uint32_t ctx_curr; > +#ifdef RTE_LIB_SECURITY > + uint8_t using_ipsec; /**< indicates that IPsec TX featu > re is in use */ > +#endif > + }; > }; > }; > I prefer solutions where the extra 80 bytes are only allocated for the one driver that needs them. I'll see if this alternative can work ok for us. /Bruce