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\ > } while(0) > +#else > +#define rte_compiler_barrier() _ReadWriteBarrier() > +#endif > > /** > * Synchronization fence between threads based on the specified memory order. > diff --git a/lib/eal/x86/include/rte_atomic.h b/lib/eal/x86/include/rte_atomic.h > index f2ee1a9..ca733c5 100644 > --- a/lib/eal/x86/include/rte_atomic.h > +++ b/lib/eal/x86/include/rte_atomic.h > @@ -28,7 +28,6 @@ > #define rte_rmb() _mm_lfence() > > #define rte_smp_wmb() rte_compiler_barrier() > - ^^ unnecessary drop > #define rte_smp_rmb() rte_compiler_barrier() > > /* > @@ -66,11 +65,15 @@ > static __rte_always_inline void > rte_smp_mb(void) > { > +#ifndef RTE_TOOLCHAIN_MSVC > #ifdef RTE_ARCH_I686 > asm volatile("lock addl $0, -128(%%esp); " ::: "memory"); > #else > asm volatile("lock addl $0, -128(%%rsp); " ::: "memory"); > #endif > +#else > + _mm_mfence(); > +#endif > } > > #define rte_io_mb() rte_mb() > -- > 1.8.3.1 >