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Fri, 6 Oct 2023 12:20:03 +0000 Date: Fri, 6 Oct 2023 13:19:58 +0100 From: Bruce Richardson To: Mattias =?iso-8859-1?Q?R=F6nnblom?= CC: , Jerin Jacob Subject: Re: [RFC PATCH] eventdev: ensure 16-byte alignment for events Message-ID: References: <20231005115101.12276-1-bruce.richardson@intel.com> Content-Type: text/plain; charset="iso-8859-1" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-ClientProxiedBy: DUZPR01CA0230.eurprd01.prod.exchangelabs.com (2603:10a6:10:4b4::7) To CY8PR11MB7290.namprd11.prod.outlook.com (2603:10b6:930:9a::6) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY8PR11MB7290:EE_|SA1PR11MB8326:EE_ X-MS-Office365-Filtering-Correlation-Id: df156076-c07e-4b93-1517-08dbc66691bb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /pKn9OFiNCMdljOXuXLHGcCGYT8bzm9eZig0qiQtOntTmxQzulA+mA/iumNdYqSnn22KpRyDH7OWoE4txW4AepxyLn0YywFlRaApvdR7Zuf65lHRqKkkZxxMinEBbo65UYhO+1JmpkkWV9wZs35QtppUHqu9Zztp9ffwYjB8gVjrQ6r9MPANTym3eF16XxiZNwVVvPH5JR+qOEeUF7bRGUdTjKa2HkWmo70HjM2qCTmdSQtLWF8KX0jA9JdkI8+M5GDz4hHogGEe8EHzLnlv6erBPSMl5CgzGo/qpUjof7QaQMikQ6R3QCT/VlABEjdIFuxEt/riYALO1jKWFSs7nxQfGO8Cke1o5qDNGZeXBdeqbz4/9lfqNhHYhAdyAQIoAuRdKN9aV70A/XzDW41xz9xW9MVl5C7mQ+2XyUcF6XC9IHu9+CFqoroCiNMNy59H/a6hwgAVru8s2wVgASz38lHyiCInLw+6hv+LA00c8o/Hui2/IvRrQoPyQ7X0qnERbMUD9hgc1ZM5xSXBAvYK5vWhgyf48SV4G4E1MBtxkZctKHZsoBByQncmXtKt2nDl X-Forefront-Antispam-Report: CIP:255.255.255.255; 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There are no such > examples in the public eventdev API. > > To help compiler optimize correctly, we can explicitly request > > 16-byte alignment for events, which means that we should be able > > to do aligned vector loads/stores (e.g. with SSE or Neon) when working > > with those events. > > > > That change is both helping and sabotaging the optimizer's work. Now every > stack allocation needs to be 2-byte aligned - in DPDK code, and in the > application. > > The effect this change has on an eventdev app using DSW is a ~3 cycle/event > performance degradation on an AMD Zen 3 system, and a ~4 cycle/event > performance degradation on a Skylake-generation Intel CPU. > Thanks for checking - this is the sort of feedback needed alright. In SW eventdev we copy events around alot without using pointers, so I felt that alignment would be helpful to avoid issues with events spanning cachelines. However, since it has negative impacts, I'm quite happy to drop the idea, and keep things as they are. I'll mark the change as rejected in patchwork. /Bruce