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Fri, 3 Nov 2023 17:16:13 +0000 Date: Fri, 3 Nov 2023 17:16:06 +0000 From: Bruce Richardson To: Abdullah Sevincer CC: , , , Subject: Re: [PATCH v1] bus/pci: add function to enable/disable PASID Message-ID: References: <20231103170347.2790525-1-abdullah.sevincer@intel.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20231103170347.2790525-1-abdullah.sevincer@intel.com> X-ClientProxiedBy: DUZPR01CA0033.eurprd01.prod.exchangelabs.com (2603:10a6:10:468::8) To DS0PR11MB7309.namprd11.prod.outlook.com (2603:10b6:8:13e::17) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR11MB7309:EE_|BN9PR11MB5324:EE_ X-MS-Office365-Filtering-Correlation-Id: 45b48a2b-7153-41d8-927d-08dbdc9094db X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: w94R6XC3HWZ5lOdY9bIJFMHf0Su48wjIqACbO5S2Niz9l1sv3jAEDSaUHYYT81cYj8/tMjuc2CSSgHDmrssCx1ocjrynh9J1pARfCF7ur/xXleey20VIes4YeXc00M6CpDsYz7VIkqxxh78aCJms8zansWJt7n/tlonS8Xri35Sd/k1HNqlrpXdK9xbh6y9jdWDT9aiUTtKr2a+P64A1b5+KFMlcOTlL/eD2Y7O91YylmegWVzoLCVgKftqyXwpXsuoHMa/7seFR/ZK2C2JvTVV4C6ojPHpONol0HoiCMtaPnXDi/M4GSlBIpjv8O/loywAGgSeyNAf5h0puQQHunI2brXFhWSeUFE8w9VVHyfU2ugJ2W/bXqQ6EdqEJgN69Ms3Jb3yL3F92WFlfX8IDZlOd0OIPCc9W5FH/Hm1fES3uNHMeHBemLxkLpqcdKvnrKA4v/18ncPmn+ykgBFoC+ZbCki0b1YD4YKhfCQCRX1UOwqCPNY+zcJ8uLJNR/hc7tngNnEPnMmiMsRjAIwbG0J61SQeqxxQi2KPDx9euc1PWLUT/BiaUfr8OpEVadL4Fsi0wTrkU6vTPkNsP80FseN9p3geiPo6nB6mvKPGEeofztXkRVIaRqE8jzCbQfuse X-Forefront-Antispam-Report: CIP:255.255.255.255; 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Therefore, api implemented in this commit accepts > an offset for PASID with an enable flag which is used > to enable/disable PASID. Lines in the commit log can go up to 72 characters, so you can be a bit less strict in wrapping. :-) The term DLB may not be familiar to everyone, so I suggest referring to it via proper name, or refer to the device driver event/dlb. Few other minor comments inline. /Bruce > > Signed-off-by: Abdullah Sevincer > --- > drivers/bus/pci/pci_common.c | 7 +++++++ > drivers/bus/pci/rte_bus_pci.h | 11 +++++++++++ > drivers/bus/pci/version.map | 1 + > lib/pci/rte_pci.h | 5 +++++ > 4 files changed, 24 insertions(+) > > diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c > index 921d957bf6..ced072825e 100644 > --- a/drivers/bus/pci/pci_common.c > +++ b/drivers/bus/pci/pci_common.c > @@ -938,6 +938,13 @@ rte_pci_set_bus_master(const struct rte_pci_device *dev, bool enable) > return 0; > } > > +int > +rte_pci_set_pasid(const struct rte_pci_device *dev, off_t offset, bool enable) > +{ > + uint16_t pasid = enable; > + return rte_pci_write_config(dev, &pasid, sizeof(pasid), offset) < 0 ? -1 : 0; > +} > + > struct rte_pci_bus rte_pci_bus = { > .bus = { > .scan = rte_pci_scan, > diff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h > index 21e234abf0..d97c8320a7 100644 > --- a/drivers/bus/pci/rte_bus_pci.h > +++ b/drivers/bus/pci/rte_bus_pci.h > @@ -295,6 +295,17 @@ void rte_pci_ioport_read(struct rte_pci_ioport *p, > void rte_pci_ioport_write(struct rte_pci_ioport *p, > const void *data, size_t len, off_t offset); > > +/** > + * Enable/Disable PASID. > + * > + * @param offset > + * Offset of the PASID external capability. > + * @param enable > + * Flag to enable or disable PASID. > + */ Missing parameter "dev". > +__rte_internal > +int rte_pci_set_pasid(const struct rte_pci_device *dev, off_t offset, bool enable); > + > #ifdef __cplusplus > } > #endif > diff --git a/drivers/bus/pci/version.map b/drivers/bus/pci/version.map > index 74c5b075d5..329d386c85 100644 > --- a/drivers/bus/pci/version.map > +++ b/drivers/bus/pci/version.map > @@ -38,4 +38,5 @@ INTERNAL { > rte_pci_get_sysfs_path; > rte_pci_register; > rte_pci_unregister; > + rte_pci_set_pasid; Keep list in alphabetical order, so new entry goes above unregister. > }; > diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h > index 69e932d910..772a8d5622 100644 > --- a/lib/pci/rte_pci.h > +++ b/lib/pci/rte_pci.h > @@ -101,6 +101,11 @@ extern "C" { > #define RTE_PCI_EXT_CAP_ID_ACS 0x0d /* Access Control Services */ > #define RTE_PCI_EXT_CAP_ID_SRIOV 0x10 /* SR-IOV */ > #define RTE_PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ > +#define RTE_PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ > + > +/* Process Address Space ID */ > +#define RTE_PCI_PASID_CTRL 0x06 /* PASID control register */ > +#define RTE_PCI_PASID_CAP_OFFSET 0x148 /* PASID capability offset */ > > /* Advanced Error Reporting (RTE_PCI_EXT_CAP_ID_ERR) */ > #define RTE_PCI_ERR_UNCOR_STATUS 0x04 /* Uncorrectable Error Status */ > -- > 2.25.1 >