From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DEB65A0508; Mon, 9 May 2022 03:35:39 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 869784068F; Mon, 9 May 2022 03:35:39 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id 000A740395 for ; Mon, 9 May 2022 03:35:36 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652060137; x=1683596137; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=50u9B2laHMWEsc4lw/iUrmGSQOeFZyKcc9aZqqc0vyg=; b=KQHZPRdUcFt7TNq0F31m9Jz++f/oG2jcyOpZxLEGKrcx0sTAMJ2aT5oG 6wDAp4O9LzihNJpdPUESe/bQcoALgPXDdmUzVbyE1znWPi0P6AQVYlnB6 jy6Xdct7wukkYbjxQ+foBEUJEjJCTfvxl+RirOVFSn1RfMCD7A8r6P3H/ G3Ga+JpBC9ocExAtY2YYoPOaqieDSOKplE4UsKHdEwgBx74Bj2vk+Fx/H yBwMnnMTHsIhLzg7xfjnjueByZuytofxjvcuScSzRoEhbulCAcm9vqANK rK0Bozn8cCAvq6tiZ6DtKvZQmhD8hlrlXegK/erjmudGdI0KtQdRG36T6 g==; X-IronPort-AV: E=McAfee;i="6400,9594,10341"; a="268826275" X-IronPort-AV: E=Sophos;i="5.91,210,1647327600"; d="scan'208";a="268826275" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2022 18:35:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,210,1647327600"; d="scan'208";a="564794216" Received: from fmsmsx605.amr.corp.intel.com ([10.18.126.85]) by orsmga007.jf.intel.com with ESMTP; 08 May 2022 18:35:35 -0700 Received: from fmsmsx610.amr.corp.intel.com (10.18.126.90) by fmsmsx605.amr.corp.intel.com (10.18.126.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27; Sun, 8 May 2022 18:35:35 -0700 Received: from fmsmsx612.amr.corp.intel.com (10.18.126.92) by fmsmsx610.amr.corp.intel.com (10.18.126.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27; Sun, 8 May 2022 18:35:34 -0700 Received: from fmsmsx612.amr.corp.intel.com ([10.18.126.92]) by fmsmsx612.amr.corp.intel.com ([10.18.126.92]) with mapi id 15.01.2308.027; Sun, 8 May 2022 18:35:34 -0700 From: "Zhang, Qi Z" To: "Zhang, Ke1X" , "Li, Xiaoyun" , "Wu, Jingjing" , "Xing, Beilei" , "dev@dpdk.org" CC: "Zhang, Ke1X" Subject: RE: [PATCH v3] fix mbuf release function point corrupt in multi-process Thread-Topic: [PATCH v3] fix mbuf release function point corrupt in multi-process Thread-Index: AQHYY0OQdxtJXV1Gwki0eugExk5I7a0VwcmA Date: Mon, 9 May 2022 01:35:34 +0000 Message-ID: References: <20220414092902.176462-1-ke1x.zhang@intel.com> <20220509011629.105267-1-ke1x.zhang@intel.com> In-Reply-To: <20220509011629.105267-1-ke1x.zhang@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.6.401.20 dlp-product: dlpe-windows x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: Ke Zhang > Sent: Monday, May 9, 2022 9:16 AM > To: Li, Xiaoyun ; Wu, Jingjing ; > Xing, Beilei ; dev@dpdk.org > Cc: Zhang, Ke1X > Subject: [PATCH v3] fix mbuf release function point corrupt in multi-proc= ess >=20 > In the multi process environment, the sub process operates on the shared > memory and changes the function pointer of the main process, resulting in= the > failure to find the address of the function when main process releasing, > resulting in crash. >=20 > Signed-off-by: Ke Zhang > --- > drivers/net/iavf/iavf_rxtx.c | 50 ++++++++++++++++++++----- > drivers/net/iavf/iavf_rxtx.h | 12 ++++++ > drivers/net/iavf/iavf_rxtx_vec_avx512.c | 8 +--- > drivers/net/iavf/iavf_rxtx_vec_sse.c | 16 ++------ > 4 files changed, 58 insertions(+), 28 deletions(-) >=20 > diff --git a/drivers/net/iavf/iavf_rxtx.c b/drivers/net/iavf/iavf_rxtx.c = index > 16e8d021f9..8d7f3c4316 100644 > --- a/drivers/net/iavf/iavf_rxtx.c > +++ b/drivers/net/iavf/iavf_rxtx.c > @@ -362,14 +362,44 @@ release_txq_mbufs(struct iavf_tx_queue *txq) > } > } >=20 > -static const struct iavf_rxq_ops def_rxq_ops =3D { > +static const > +struct iavf_rxq_ops def_rxq_ops =3D { > .release_mbufs =3D release_rxq_mbufs, > }; >=20 > -static const struct iavf_txq_ops def_txq_ops =3D { > +static const > +struct iavf_txq_ops def_txq_ops =3D { > .release_mbufs =3D release_txq_mbufs, > }; >=20 > +static const > +struct iavf_rxq_ops sse_vec_rxq_ops =3D { > + .release_mbufs =3D iavf_rx_queue_release_mbufs_sse, }; > + > +static const > +struct iavf_txq_ops sse_vec_txq_ops =3D { > + .release_mbufs =3D iavf_tx_queue_release_mbufs_sse, }; > + > +static const > +struct iavf_txq_ops avx512_vec_txq_ops =3D { > + .release_mbufs =3D iavf_tx_queue_release_mbufs_avx512, > +}; > + > +static const > +struct iavf_rxq_ops iavf_rxq_release_mbufs_ops[IAVF_REL_MBUFS_LAST + 1] > =3D { > + [IAVF_REL_MBUFS_NORMAL] =3D def_rxq_ops, > + [IAVF_REL_MBUFS_VEC] =3D sse_vec_rxq_ops, }; Please name the macro align with the ops name, replace NORMAL with DEFAULT = and VEC with SSE > + > +static const > +struct iavf_txq_ops iavf_txq_release_mbufs_ops[IAVF_REL_MBUFS_LAST + 1] > =3D { > + [IAVF_REL_MBUFS_NORMAL] =3D def_txq_ops, > + [IAVF_REL_MBUFS_VEC_AVX512] =3D avx512_vec_txq_ops, > + [IAVF_REL_MBUFS_VEC] =3D sse_vec_txq_ops, }; Please re-order it to align with Rx, default -> sse -> avx512. > + > static inline void > iavf_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct iavf_rx_queue > *rxq, > struct rte_mbuf *mb, > @@ -674,7 +704,7 @@ iavf_dev_rx_queue_setup(struct rte_eth_dev *dev, > uint16_t queue_idx, > rxq->q_set =3D true; > dev->data->rx_queues[queue_idx] =3D rxq; > rxq->qrx_tail =3D hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id); > - rxq->ops =3D &def_rxq_ops; > + rxq->rel_mbufs_type =3D IAVF_REL_MBUFS_NORMAL; >=20 > if (check_rx_bulk_allow(rxq) =3D=3D true) { > PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are > " > @@ -811,7 +841,7 @@ iavf_dev_tx_queue_setup(struct rte_eth_dev *dev, > txq->q_set =3D true; > dev->data->tx_queues[queue_idx] =3D txq; > txq->qtx_tail =3D hw->hw_addr + IAVF_QTX_TAIL1(queue_idx); > - txq->ops =3D &def_txq_ops; > + txq->rel_mbufs_type =3D IAVF_REL_MBUFS_NORMAL; >=20 > if (check_tx_vec_allow(txq) =3D=3D false) { > struct iavf_adapter *ad =3D > @@ -943,7 +973,7 @@ iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, > uint16_t rx_queue_id) > } >=20 > rxq =3D dev->data->rx_queues[rx_queue_id]; > - rxq->ops->release_mbufs(rxq); > + iavf_rxq_release_mbufs_ops[rxq->rel_mbufs_type].release_mbufs(rxq); > reset_rx_queue(rxq); > dev->data->rx_queue_state[rx_queue_id] =3D > RTE_ETH_QUEUE_STATE_STOPPED; >=20 > @@ -971,7 +1001,7 @@ iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, > uint16_t tx_queue_id) > } >=20 > txq =3D dev->data->tx_queues[tx_queue_id]; > - txq->ops->release_mbufs(txq); > + iavf_txq_release_mbufs_ops[txq->rel_mbufs_type].release_mbufs(txq); > reset_tx_queue(txq); > dev->data->tx_queue_state[tx_queue_id] =3D > RTE_ETH_QUEUE_STATE_STOPPED; >=20 > @@ -986,7 +1016,7 @@ iavf_dev_rx_queue_release(struct rte_eth_dev *dev, > uint16_t qid) > if (!q) > return; >=20 > - q->ops->release_mbufs(q); > + iavf_rxq_release_mbufs_ops[q->rel_mbufs_type].release_mbufs(q); > rte_free(q->sw_ring); > rte_memzone_free(q->mz); > rte_free(q); > @@ -1000,7 +1030,7 @@ iavf_dev_tx_queue_release(struct rte_eth_dev *dev, > uint16_t qid) > if (!q) > return; >=20 > - q->ops->release_mbufs(q); > + iavf_txq_release_mbufs_ops[q->rel_mbufs_type].release_mbufs(q); > rte_free(q->sw_ring); > rte_memzone_free(q->mz); > rte_free(q); > @@ -1034,7 +1064,7 @@ iavf_stop_queues(struct rte_eth_dev *dev) > txq =3D dev->data->tx_queues[i]; > if (!txq) > continue; > - txq->ops->release_mbufs(txq); > + iavf_txq_release_mbufs_ops[txq- > >rel_mbufs_type].release_mbufs(txq); > reset_tx_queue(txq); > dev->data->tx_queue_state[i] =3D > RTE_ETH_QUEUE_STATE_STOPPED; > } > @@ -1042,7 +1072,7 @@ iavf_stop_queues(struct rte_eth_dev *dev) > rxq =3D dev->data->rx_queues[i]; > if (!rxq) > continue; > - rxq->ops->release_mbufs(rxq); > + iavf_rxq_release_mbufs_ops[rxq- > >rel_mbufs_type].release_mbufs(rxq); > reset_rx_queue(rxq); > dev->data->rx_queue_state[i] =3D > RTE_ETH_QUEUE_STATE_STOPPED; > } > diff --git a/drivers/net/iavf/iavf_rxtx.h b/drivers/net/iavf/iavf_rxtx.h = index > bf8aebbce8..826f59da39 100644 > --- a/drivers/net/iavf/iavf_rxtx.h > +++ b/drivers/net/iavf/iavf_rxtx.h > @@ -187,6 +187,7 @@ struct iavf_rx_queue { > struct rte_mbuf *pkt_last_seg; /* last segment of current packet */ > struct rte_mbuf fake_mbuf; /* dummy mbuf */ > uint8_t rxdid; > + uint8_t rel_mbufs_type; >=20 > /* used for VPMD */ > uint16_t rxrearm_nb; /* number of remaining to be re-armed */ > @@ -246,6 +247,7 @@ struct iavf_tx_queue { > uint16_t last_desc_cleaned; /* last desc have been cleaned*/ > uint16_t free_thresh; > uint16_t rs_thresh; > + uint8_t rel_mbufs_type; >=20 > uint16_t port_id; > uint16_t queue_id; > @@ -389,6 +391,13 @@ struct iavf_32b_rx_flex_desc_comms_ipsec { > __le32 ipsec_said; > }; >=20 > +enum iavf_rxtx_rel_mbufs_type { > + IAVF_REL_MBUFS_NORMAL =3D 0, > + IAVF_REL_MBUFS_VEC_AVX512 =3D 1, > + IAVF_REL_MBUFS_VEC =3D 2, > + IAVF_REL_MBUFS_LAST =3D 63, IAVF_REL_MBUFS_LAST is not necessary.