* [dpdk-dev] [PATCH v4 0/6] net: ngbe PMD
@ 2021-04-06 9:30 Jiawen Wu
2021-04-06 9:30 ` [dpdk-dev] [PATCH v4 1/6] net/ngbe: add build and doc infrastructure Jiawen Wu
` (6 more replies)
0 siblings, 7 replies; 14+ messages in thread
From: Jiawen Wu @ 2021-04-06 9:30 UTC (permalink / raw)
To: dev; +Cc: Jiawen Wu
This patch set provides a skeleton of ngbe PMD,
which adapted to Wangxun WX1860 series NICs.
v4:
- Fix compile error.
v3:
- Use rte_ether functions to define marcos.
v2:
- Correct some clerical errors.
- Use ethdev debug flags instead of driver own.
Jiawen Wu (6):
net/ngbe: add build and doc infrastructure
net/ngbe: add device IDs
net/ngbe: support probe and remove
net/ngbe: add device init and uninit
net/ngbe: add log type and error type
net/ngbe: define registers
MAINTAINERS | 6 +
doc/guides/nics/features/ngbe.ini | 11 +
doc/guides/nics/index.rst | 1 +
doc/guides/nics/ngbe.rst | 48 +
doc/guides/rel_notes/release_21_05.rst | 6 +
drivers/net/meson.build | 1 +
drivers/net/ngbe/base/meson.build | 20 +
drivers/net/ngbe/base/ngbe.h | 11 +
drivers/net/ngbe/base/ngbe_devids.h | 83 ++
drivers/net/ngbe/base/ngbe_hw.c | 59 +
drivers/net/ngbe/base/ngbe_hw.h | 12 +
drivers/net/ngbe/base/ngbe_osdep.h | 174 +++
drivers/net/ngbe/base/ngbe_regs.h | 1489 ++++++++++++++++++++++++
drivers/net/ngbe/base/ngbe_status.h | 124 ++
drivers/net/ngbe/base/ngbe_type.h | 30 +
drivers/net/ngbe/meson.build | 18 +
drivers/net/ngbe/ngbe_ethdev.c | 156 +++
drivers/net/ngbe/ngbe_ethdev.h | 21 +
drivers/net/ngbe/ngbe_logs.h | 45 +
drivers/net/ngbe/version.map | 3 +
20 files changed, 2318 insertions(+)
create mode 100644 doc/guides/nics/features/ngbe.ini
create mode 100644 doc/guides/nics/ngbe.rst
create mode 100644 drivers/net/ngbe/base/meson.build
create mode 100644 drivers/net/ngbe/base/ngbe.h
create mode 100644 drivers/net/ngbe/base/ngbe_devids.h
create mode 100644 drivers/net/ngbe/base/ngbe_hw.c
create mode 100644 drivers/net/ngbe/base/ngbe_hw.h
create mode 100644 drivers/net/ngbe/base/ngbe_osdep.h
create mode 100644 drivers/net/ngbe/base/ngbe_regs.h
create mode 100644 drivers/net/ngbe/base/ngbe_status.h
create mode 100644 drivers/net/ngbe/base/ngbe_type.h
create mode 100644 drivers/net/ngbe/meson.build
create mode 100644 drivers/net/ngbe/ngbe_ethdev.c
create mode 100644 drivers/net/ngbe/ngbe_ethdev.h
create mode 100644 drivers/net/ngbe/ngbe_logs.h
create mode 100644 drivers/net/ngbe/version.map
--
2.21.0.windows.1
^ permalink raw reply [flat|nested] 14+ messages in thread* [dpdk-dev] [PATCH v4 1/6] net/ngbe: add build and doc infrastructure 2021-04-06 9:30 [dpdk-dev] [PATCH v4 0/6] net: ngbe PMD Jiawen Wu @ 2021-04-06 9:30 ` Jiawen Wu 2021-04-09 14:37 ` Ferruh Yigit 2021-04-06 9:30 ` [dpdk-dev] [PATCH v4 2/6] net/ngbe: add device IDs Jiawen Wu ` (5 subsequent siblings) 6 siblings, 1 reply; 14+ messages in thread From: Jiawen Wu @ 2021-04-06 9:30 UTC (permalink / raw) To: dev; +Cc: Jiawen Wu Adding bare minimum PMD library and doc build infrastructure and claim the maintainership for ngbe PMD. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> --- MAINTAINERS | 6 ++++++ doc/guides/nics/features/ngbe.ini | 10 +++++++++ doc/guides/nics/index.rst | 1 + doc/guides/nics/ngbe.rst | 28 ++++++++++++++++++++++++++ doc/guides/rel_notes/release_21_05.rst | 6 ++++++ drivers/net/meson.build | 1 + drivers/net/ngbe/meson.build | 12 +++++++++++ drivers/net/ngbe/ngbe_ethdev.c | 4 ++++ drivers/net/ngbe/ngbe_ethdev.h | 4 ++++ drivers/net/ngbe/version.map | 3 +++ 10 files changed, 75 insertions(+) create mode 100644 doc/guides/nics/features/ngbe.ini create mode 100644 doc/guides/nics/ngbe.rst create mode 100644 drivers/net/ngbe/meson.build create mode 100644 drivers/net/ngbe/ngbe_ethdev.c create mode 100644 drivers/net/ngbe/ngbe_ethdev.h create mode 100644 drivers/net/ngbe/version.map diff --git a/MAINTAINERS b/MAINTAINERS index 0ec558854..d3007aac5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -887,6 +887,12 @@ F: drivers/net/txgbe/ F: doc/guides/nics/txgbe.rst F: doc/guides/nics/features/txgbe.ini +Wangxun ngbe +M: Jiawen Wu <jiawenwu@trustnetic.com> +F: drivers/net/ngbe/ +F: doc/guides/nics/ngbe.rst +F: doc/guides/nics/features/ngbe.ini + VMware vmxnet3 M: Yong Wang <yongwang@vmware.com> F: drivers/net/vmxnet3/ diff --git a/doc/guides/nics/features/ngbe.ini b/doc/guides/nics/features/ngbe.ini new file mode 100644 index 000000000..a7a524def --- /dev/null +++ b/doc/guides/nics/features/ngbe.ini @@ -0,0 +1,10 @@ +; +; Supported features of the 'ngbe' network poll mode driver. +; +; Refer to default.ini for the full list of available PMD features. +; +[Features] +Linux = Y +ARMv8 = Y +x86-32 = Y +x86-64 = Y diff --git a/doc/guides/nics/index.rst b/doc/guides/nics/index.rst index 799697caf..31a3e6bcd 100644 --- a/doc/guides/nics/index.rst +++ b/doc/guides/nics/index.rst @@ -47,6 +47,7 @@ Network Interface Controller Drivers netvsc nfb nfp + ngbe null octeontx octeontx2 diff --git a/doc/guides/nics/ngbe.rst b/doc/guides/nics/ngbe.rst new file mode 100644 index 000000000..007d8e80e --- /dev/null +++ b/doc/guides/nics/ngbe.rst @@ -0,0 +1,28 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2018-2020. + +NGBE Poll Mode Driver +====================== + +The NGBE PMD (librte_pmd_ngbe) provides poll mode driver support +for Wangxun 1 Gigabit Ethernet NICs. + +Prerequisites +------------- + +- Learning about Wangxun 10 Gigabit Ethernet NICs using + `<https://www.net-swift.com/a/386.html>`_. + +- Follow the DPDK :ref:`Getting Started Guide for Linux <linux_gsg>` to setup the basic DPDK environment. + +Driver compilation and testing +------------------------------ + +Refer to the document :ref:`compiling and testing a PMD for a NIC <pmd_build_and_test>` +for details. + +Limitations or Known issues +--------------------------- + +Build with ICC is not supported yet. +Power8, ARMv7 and BSD are not supported yet. diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index 19cec62c7..ad7a9d286 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -113,6 +113,12 @@ New Features * Added support for txgbevf PMD. * Support device arguments to handle AN training for backplane NICs. +* **Added Wangxun ngbe PMD.** + + Added a new PMD driver for Wangxun 1 Gigabit Ethernet NICs. + + See the :doc:`../nics/ngbe` for more details. + * **Enabled vmxnet3 PMD on Windows.** * **Updated the AF_XDP driver.** diff --git a/drivers/net/meson.build b/drivers/net/meson.build index fb9ff05a1..d1baa2842 100644 --- a/drivers/net/meson.build +++ b/drivers/net/meson.build @@ -36,6 +36,7 @@ drivers = ['af_packet', 'netvsc', 'nfb', 'nfp', + 'ngbe', 'null', 'octeontx', 'octeontx2', diff --git a/drivers/net/ngbe/meson.build b/drivers/net/ngbe/meson.build new file mode 100644 index 000000000..d6388d061 --- /dev/null +++ b/drivers/net/ngbe/meson.build @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018-2020 + +if is_windows + build = false + reason = 'not supported on Windows' + subdir_done() +endif + +sources = files( + 'ngbe_ethdev.c', +) diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c new file mode 100644 index 000000000..e2756315a --- /dev/null +++ b/drivers/net/ngbe/ngbe_ethdev.c @@ -0,0 +1,4 @@ + /* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018-2020 + */ + diff --git a/drivers/net/ngbe/ngbe_ethdev.h b/drivers/net/ngbe/ngbe_ethdev.h new file mode 100644 index 000000000..20f37e9d4 --- /dev/null +++ b/drivers/net/ngbe/ngbe_ethdev.h @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018-2020 + */ + diff --git a/drivers/net/ngbe/version.map b/drivers/net/ngbe/version.map new file mode 100644 index 000000000..4a76d1d52 --- /dev/null +++ b/drivers/net/ngbe/version.map @@ -0,0 +1,3 @@ +DPDK_21 { + local: *; +}; -- 2.21.0.windows.1 ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [dpdk-dev] [PATCH v4 1/6] net/ngbe: add build and doc infrastructure 2021-04-06 9:30 ` [dpdk-dev] [PATCH v4 1/6] net/ngbe: add build and doc infrastructure Jiawen Wu @ 2021-04-09 14:37 ` Ferruh Yigit 2021-04-12 6:33 ` Jiawen Wu 0 siblings, 1 reply; 14+ messages in thread From: Ferruh Yigit @ 2021-04-09 14:37 UTC (permalink / raw) To: Jiawen Wu, dev On 4/6/2021 10:30 AM, Jiawen Wu wrote: > Adding bare minimum PMD library and doc build infrastructure > and claim the maintainership for ngbe PMD. > > Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> <...> > diff --git a/doc/guides/nics/ngbe.rst b/doc/guides/nics/ngbe.rst > new file mode 100644 > index 000000000..007d8e80e > --- /dev/null > +++ b/doc/guides/nics/ngbe.rst > @@ -0,0 +1,28 @@ > +.. SPDX-License-Identifier: BSD-3-Clause > + Copyright(c) 2018-2020. You may want to add who is the copyright owner, like "Intel Corporation" part in Copyright(c) 2017-2019 Intel Corporation I recognized same is missing in txgbe too, can you fix that too please? > + > +NGBE Poll Mode Driver > +====================== > + > +The NGBE PMD (librte_pmd_ngbe) provides poll mode driver support > +for Wangxun 1 Gigabit Ethernet NICs. > + > +Prerequisites > +------------- > + > +- Learning about Wangxun 10 Gigabit Ethernet NICs using "10 Gigabit" or "1 Gigabit"? > + `<https://www.net-swift.com/a/386.html>`_. > + What is the relation between netswift/WebEx/Wangxun ? ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [dpdk-dev] [PATCH v4 1/6] net/ngbe: add build and doc infrastructure 2021-04-09 14:37 ` Ferruh Yigit @ 2021-04-12 6:33 ` Jiawen Wu 0 siblings, 0 replies; 14+ messages in thread From: Jiawen Wu @ 2021-04-12 6:33 UTC (permalink / raw) To: 'Ferruh Yigit', dev On April 9, 2021 10:37 PM, Ferruh Yigit wrote: > On 4/6/2021 10:30 AM, Jiawen Wu wrote: > > Adding bare minimum PMD library and doc build infrastructure and claim > > the maintainership for ngbe PMD. > > > > Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> > > <...> > > > diff --git a/doc/guides/nics/ngbe.rst b/doc/guides/nics/ngbe.rst new > > file mode 100644 index 000000000..007d8e80e > > --- /dev/null > > +++ b/doc/guides/nics/ngbe.rst > > @@ -0,0 +1,28 @@ > > +.. SPDX-License-Identifier: BSD-3-Clause > > + Copyright(c) 2018-2020. > > You may want to add who is the copyright owner, like "Intel Corporation" part > in > Copyright(c) 2017-2019 Intel Corporation > > I recognized same is missing in txgbe too, can you fix that too please? > I'm thinking about it... > > + > > +NGBE Poll Mode Driver > > +====================== > > + > > +The NGBE PMD (librte_pmd_ngbe) provides poll mode driver support for > > +Wangxun 1 Gigabit Ethernet NICs. > > + > > +Prerequisites > > +------------- > > + > > +- Learning about Wangxun 10 Gigabit Ethernet NICs using > > "10 Gigabit" or "1 Gigabit"? > It's a clerical error. > > + `<https://www.net-swift.com/a/386.html>`_. > > + > > What is the relation between netswift/WebEx/Wangxun ? Wangxun is Chinese spell of our company name, trustnetic and net-swift are domain names. WebEx, as far as I know, its Chinese translation is the same as Wangxun, but it has nothing relation between us. ^ permalink raw reply [flat|nested] 14+ messages in thread
* [dpdk-dev] [PATCH v4 2/6] net/ngbe: add device IDs 2021-04-06 9:30 [dpdk-dev] [PATCH v4 0/6] net: ngbe PMD Jiawen Wu 2021-04-06 9:30 ` [dpdk-dev] [PATCH v4 1/6] net/ngbe: add build and doc infrastructure Jiawen Wu @ 2021-04-06 9:30 ` Jiawen Wu 2021-04-09 14:37 ` Ferruh Yigit 2021-04-06 9:30 ` [dpdk-dev] [PATCH v4 3/6] net/ngbe: support probe and remove Jiawen Wu ` (4 subsequent siblings) 6 siblings, 1 reply; 14+ messages in thread From: Jiawen Wu @ 2021-04-06 9:30 UTC (permalink / raw) To: dev; +Cc: Jiawen Wu Add device IDs for Wangxun 1Gb NICs, and register rte_ngbe_pmd. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> --- drivers/net/ngbe/base/meson.build | 18 +++++++ drivers/net/ngbe/base/ngbe_devids.h | 83 +++++++++++++++++++++++++++++ drivers/net/ngbe/meson.build | 6 +++ drivers/net/ngbe/ngbe_ethdev.c | 33 ++++++++++++ 4 files changed, 140 insertions(+) create mode 100644 drivers/net/ngbe/base/meson.build create mode 100644 drivers/net/ngbe/base/ngbe_devids.h diff --git a/drivers/net/ngbe/base/meson.build b/drivers/net/ngbe/base/meson.build new file mode 100644 index 000000000..b4fc6a53b --- /dev/null +++ b/drivers/net/ngbe/base/meson.build @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018-2020 + +sources = [] + +error_cflags = [] + +c_args = cflags +foreach flag: error_cflags + if cc.has_argument(flag) + c_args += flag + endif +endforeach + +base_lib = static_library('ngbe_base', sources, + dependencies: [static_rte_eal, static_rte_ethdev, static_rte_bus_pci], + c_args: c_args) +base_objs = base_lib.extract_all_objects() diff --git a/drivers/net/ngbe/base/ngbe_devids.h b/drivers/net/ngbe/base/ngbe_devids.h new file mode 100644 index 000000000..79967b9fe --- /dev/null +++ b/drivers/net/ngbe/base/ngbe_devids.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018-2020 + */ + +#ifndef _NGBE_DEVIDS_H_ +#define _NGBE_DEVIDS_H_ + +/* + * Vendor ID + */ +#ifndef PCI_VENDOR_ID_WANGXUN +#define PCI_VENDOR_ID_WANGXUN 0x8088 +#endif + +/* + * Device IDs + */ +#define NGBE_DEV_ID_EM_VF 0x0110 +#define NGBE_SUB_DEV_ID_EM_VF 0x0110 +#define NGBE_DEV_ID_EM 0x0100 +#define NGBE_SUB_DEV_ID_EM_MVL_RGMII 0x0200 +#define NGBE_SUB_DEV_ID_EM_MVL_SFP 0x0403 +#define NGBE_SUB_DEV_ID_EM_RTL_SGMII 0x0410 +#define NGBE_SUB_DEV_ID_EM_YT8521S_SFP 0x0460 + +#define NGBE_DEV_ID_EM_WX1860AL_W 0x0100 +#define NGBE_DEV_ID_EM_WX1860AL_W_VF 0x0110 +#define NGBE_DEV_ID_EM_WX1860A2 0x0101 +#define NGBE_DEV_ID_EM_WX1860A2_VF 0x0111 +#define NGBE_DEV_ID_EM_WX1860A2S 0x0102 +#define NGBE_DEV_ID_EM_WX1860A2S_VF 0x0112 +#define NGBE_DEV_ID_EM_WX1860A4 0x0103 +#define NGBE_DEV_ID_EM_WX1860A4_VF 0x0113 +#define NGBE_DEV_ID_EM_WX1860A4S 0x0104 +#define NGBE_DEV_ID_EM_WX1860A4S_VF 0x0114 +#define NGBE_DEV_ID_EM_WX1860AL2 0x0105 +#define NGBE_DEV_ID_EM_WX1860AL2_VF 0x0115 +#define NGBE_DEV_ID_EM_WX1860AL2S 0x0106 +#define NGBE_DEV_ID_EM_WX1860AL2S_VF 0x0116 +#define NGBE_DEV_ID_EM_WX1860AL4 0x0107 +#define NGBE_DEV_ID_EM_WX1860AL4_VF 0x0117 +#define NGBE_DEV_ID_EM_WX1860AL4S 0x0108 +#define NGBE_DEV_ID_EM_WX1860AL4S_VF 0x0118 +#define NGBE_DEV_ID_EM_WX1860NCSI 0x0109 +#define NGBE_DEV_ID_EM_WX1860NCSI_VF 0x0119 +#define NGBE_DEV_ID_EM_WX1860A1 0x010A +#define NGBE_DEV_ID_EM_WX1860A1_VF 0x011A +#define NGBE_DEV_ID_EM_WX1860A1L 0x010B +#define NGBE_DEV_ID_EM_WX1860A1L_VF 0x011B +#define NGBE_SUB_DEV_ID_EM_ZTE5201_RJ45 0x0100 +#define NGBE_SUB_DEV_ID_EM_SF100F_LP 0x0103 +#define NGBE_SUB_DEV_ID_EM_M88E1512_RJ45 0x0200 +#define NGBE_SUB_DEV_ID_EM_SF100HT 0x0102 +#define NGBE_SUB_DEV_ID_EM_SF200T 0x0201 +#define NGBE_SUB_DEV_ID_EM_SF200HT 0x0202 +#define NGBE_SUB_DEV_ID_EM_SF200T_S 0x0210 +#define NGBE_SUB_DEV_ID_EM_SF200HT_S 0x0220 +#define NGBE_SUB_DEV_ID_EM_SF200HXT 0x0230 +#define NGBE_SUB_DEV_ID_EM_SF400T 0x0401 +#define NGBE_SUB_DEV_ID_EM_SF400HT 0x0402 +#define NGBE_SUB_DEV_ID_EM_M88E1512_SFP 0x0403 +#define NGBE_SUB_DEV_ID_EM_SF400T_S 0x0410 +#define NGBE_SUB_DEV_ID_EM_SF400HT_S 0x0420 +#define NGBE_SUB_DEV_ID_EM_SF400HXT 0x0430 +#define NGBE_SUB_DEV_ID_EM_SF400_OCP 0x0440 +#define NGBE_SUB_DEV_ID_EM_SF400_LY 0x0450 +#define NGBE_SUB_DEV_ID_EM_SF400_LY_YT 0x0470 + +/* Assign excessive id with masks */ +#define NGBE_INTERNAL_MASK 0x000F +#define NGBE_OEM_MASK 0x00F0 +#define NGBE_WOL_SUP_MASK 0x4000 +#define NGBE_NCSI_SUP_MASK 0x8000 + +#define NGBE_INTERNAL_SFP 0x0003 +#define NGBE_OCP_CARD 0x0040 +#define NGBE_LY_M88E1512_SFP 0x0050 +#define NGBE_YT8521S_SFP 0x0060 +#define NGBE_LY_YT8521S_SFP 0x0070 +#define NGBE_WOL_SUP 0x4000 +#define NGBE_NCSI_SUP 0x8000 + +#endif /* _NGBE_DEVIDS_H_ */ diff --git a/drivers/net/ngbe/meson.build b/drivers/net/ngbe/meson.build index d6388d061..0bd457c14 100644 --- a/drivers/net/ngbe/meson.build +++ b/drivers/net/ngbe/meson.build @@ -7,6 +7,12 @@ if is_windows subdir_done() endif +subdir('base') +objs = [base_objs] + sources = files( 'ngbe_ethdev.c', ) + +includes += include_directories('base') + diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c index e2756315a..da951b6ef 100644 --- a/drivers/net/ngbe/ngbe_ethdev.c +++ b/drivers/net/ngbe/ngbe_ethdev.c @@ -2,3 +2,36 @@ * Copyright(c) 2018-2020 */ +#include <ethdev_pci.h> + +#include <base/ngbe_devids.h> + +/* + * The set of PCI devices this driver supports + */ +static const struct rte_pci_id pci_id_ngbe_map[] = { + { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A2) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A2S) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A4) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A4S) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860AL2) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860AL2S) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860AL4) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860AL4S) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860NCSI) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A1) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860A1L) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, NGBE_DEV_ID_EM_WX1860AL_W) }, + { .vendor_id = 0, /* sentinel */ }, +}; + +static struct rte_pci_driver rte_ngbe_pmd = { + .id_table = pci_id_ngbe_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING | + RTE_PCI_DRV_INTR_LSC, +}; + +RTE_PMD_REGISTER_PCI(net_ngbe, rte_ngbe_pmd); +RTE_PMD_REGISTER_PCI_TABLE(net_ngbe, pci_id_ngbe_map); +RTE_PMD_REGISTER_KMOD_DEP(net_ngbe, "* igb_uio | uio_pci_generic | vfio-pci"); + -- 2.21.0.windows.1 ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [dpdk-dev] [PATCH v4 2/6] net/ngbe: add device IDs 2021-04-06 9:30 ` [dpdk-dev] [PATCH v4 2/6] net/ngbe: add device IDs Jiawen Wu @ 2021-04-09 14:37 ` Ferruh Yigit 0 siblings, 0 replies; 14+ messages in thread From: Ferruh Yigit @ 2021-04-09 14:37 UTC (permalink / raw) To: Jiawen Wu, dev On 4/6/2021 10:30 AM, Jiawen Wu wrote: > Add device IDs for Wangxun 1Gb NICs, and register rte_ngbe_pmd. > > Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> <...> > +static struct rte_pci_driver rte_ngbe_pmd = { > + .id_table = pci_id_ngbe_map, > + .drv_flags = RTE_PCI_DRV_NEED_MAPPING | > + RTE_PCI_DRV_INTR_LSC, > +}; > + > +RTE_PMD_REGISTER_PCI(net_ngbe, rte_ngbe_pmd); > +RTE_PMD_REGISTER_PCI_TABLE(net_ngbe, pci_id_ngbe_map); At this stage driver->probe() will be called if matched device found, it is unlikely that the code will be run at this stage, but anyway to not leave the code in a state that it will for sure crash, can you add the 'probe()'/'remove()' functions here even if it is empty and just returns? ^ permalink raw reply [flat|nested] 14+ messages in thread
* [dpdk-dev] [PATCH v4 3/6] net/ngbe: support probe and remove 2021-04-06 9:30 [dpdk-dev] [PATCH v4 0/6] net: ngbe PMD Jiawen Wu 2021-04-06 9:30 ` [dpdk-dev] [PATCH v4 1/6] net/ngbe: add build and doc infrastructure Jiawen Wu 2021-04-06 9:30 ` [dpdk-dev] [PATCH v4 2/6] net/ngbe: add device IDs Jiawen Wu @ 2021-04-06 9:30 ` Jiawen Wu 2021-04-09 14:40 ` Ferruh Yigit 2021-04-06 9:30 ` [dpdk-dev] [PATCH v4 4/6] net/ngbe: add device init and uninit Jiawen Wu ` (3 subsequent siblings) 6 siblings, 1 reply; 14+ messages in thread From: Jiawen Wu @ 2021-04-06 9:30 UTC (permalink / raw) To: dev; +Cc: Jiawen Wu Add basic PCIe ethdev probe and remove. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> --- doc/guides/nics/features/ngbe.ini | 1 + drivers/net/ngbe/ngbe_ethdev.c | 77 +++++++++++++++++++++++++++++-- drivers/net/ngbe/ngbe_ethdev.h | 10 ++++ 3 files changed, 85 insertions(+), 3 deletions(-) diff --git a/doc/guides/nics/features/ngbe.ini b/doc/guides/nics/features/ngbe.ini index a7a524def..977286ac0 100644 --- a/doc/guides/nics/features/ngbe.ini +++ b/doc/guides/nics/features/ngbe.ini @@ -4,6 +4,7 @@ ; Refer to default.ini for the full list of available PMD features. ; [Features] +Multiprocess aware = Y Linux = Y ARMv8 = Y x86-32 = Y diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c index da951b6ef..d938fd68a 100644 --- a/drivers/net/ngbe/ngbe_ethdev.c +++ b/drivers/net/ngbe/ngbe_ethdev.c @@ -1,10 +1,12 @@ - /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2018-2020 - */ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018-2020 + */ +#include <rte_common.h> #include <ethdev_pci.h> #include <base/ngbe_devids.h> +#include "ngbe_ethdev.h" /* * The set of PCI devices this driver supports @@ -25,10 +27,79 @@ static const struct rte_pci_id pci_id_ngbe_map[] = { { .vendor_id = 0, /* sentinel */ }, }; +static int +eth_ngbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) +{ + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + rte_eth_copy_pci_info(eth_dev, pci_dev); + + return 0; +} + +static int +eth_ngbe_dev_uninit(struct rte_eth_dev *eth_dev) +{ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + RTE_SET_USED(eth_dev); + + return 0; +} + +static int +eth_ngbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, + struct rte_pci_device *pci_dev) +{ + struct rte_eth_dev *pf_ethdev; + struct rte_eth_devargs eth_da; + int retval; + + if (pci_dev->device.devargs) { + retval = rte_eth_devargs_parse(pci_dev->device.devargs->args, + ð_da); + if (retval) + return retval; + } else { + memset(ð_da, 0, sizeof(eth_da)); + } + + retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, + sizeof(struct ngbe_adapter), + eth_dev_pci_specific_init, pci_dev, + eth_ngbe_dev_init, NULL); + + if (retval || eth_da.nb_representor_ports < 1) + return retval; + + pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name); + if (pf_ethdev == NULL) + return -ENODEV; + + return 0; +} + +static int eth_ngbe_pci_remove(struct rte_pci_device *pci_dev) +{ + struct rte_eth_dev *ethdev; + + ethdev = rte_eth_dev_allocated(pci_dev->device.name); + if (!ethdev) + return -ENODEV; + + return rte_eth_dev_destroy(ethdev, eth_ngbe_dev_uninit); +} + static struct rte_pci_driver rte_ngbe_pmd = { .id_table = pci_id_ngbe_map, .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, + .probe = eth_ngbe_pci_probe, + .remove = eth_ngbe_pci_remove, }; RTE_PMD_REGISTER_PCI(net_ngbe, rte_ngbe_pmd); diff --git a/drivers/net/ngbe/ngbe_ethdev.h b/drivers/net/ngbe/ngbe_ethdev.h index 20f37e9d4..8dab39faf 100644 --- a/drivers/net/ngbe/ngbe_ethdev.h +++ b/drivers/net/ngbe/ngbe_ethdev.h @@ -2,3 +2,13 @@ * Copyright(c) 2018-2020 */ +#ifndef _NGBE_ETHDEV_H_ +#define _NGBE_ETHDEV_H_ + +/* + * Structure to store private data for each driver instance (for each port). + */ +struct ngbe_adapter { +}; + +#endif /* _NGBE_ETHDEV_H_ */ -- 2.21.0.windows.1 ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [dpdk-dev] [PATCH v4 3/6] net/ngbe: support probe and remove 2021-04-06 9:30 ` [dpdk-dev] [PATCH v4 3/6] net/ngbe: support probe and remove Jiawen Wu @ 2021-04-09 14:40 ` Ferruh Yigit 0 siblings, 0 replies; 14+ messages in thread From: Ferruh Yigit @ 2021-04-09 14:40 UTC (permalink / raw) To: Jiawen Wu, dev On 4/6/2021 10:30 AM, Jiawen Wu wrote: > Add basic PCIe ethdev probe and remove. > > Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> <...> > --- a/drivers/net/ngbe/ngbe_ethdev.c > +++ b/drivers/net/ngbe/ngbe_ethdev.c > @@ -1,10 +1,12 @@ > - /* SPDX-License-Identifier: BSD-3-Clause > - * Copyright(c) 2018-2020 > - */ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2018-2020 > + */ Can you please fix this where it is introduced at first place? <...> > +static int > +eth_ngbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, > + struct rte_pci_device *pci_dev) > +{ > + struct rte_eth_dev *pf_ethdev; > + struct rte_eth_devargs eth_da; > + int retval; > + > + if (pci_dev->device.devargs) { > + retval = rte_eth_devargs_parse(pci_dev->device.devargs->args, > + ð_da); > + if (retval) > + return retval; > + } else { > + memset(ð_da, 0, sizeof(eth_da)); > + } > + > + retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, > + sizeof(struct ngbe_adapter), > + eth_dev_pci_specific_init, pci_dev, > + eth_ngbe_dev_init, NULL); > + > + if (retval || eth_da.nb_representor_ports < 1) > + return retval; no need to check the 'nb_representor_ports' here, the driver does not support the port anyway, it can return immediately. Similarly 'rte_eth_devargs_parse()' call above can be removed, for same reason. When port representor support added to driver, following check also may be added since new representator types are added recently. if (eth_da.type != RTE_ETH_REPRESENTOR_VF) return -ENOTSUP; > + > + pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name); > + if (pf_ethdev == NULL) > + return -ENODEV; > + Also above part can be removed completely, pf_ethdev is get to use in the existance of the port representor, no need to get it now. > + return 0; > +} > + > +static int eth_ngbe_pci_remove(struct rte_pci_device *pci_dev) > +{ > + struct rte_eth_dev *ethdev; > + > + ethdev = rte_eth_dev_allocated(pci_dev->device.name); > + if (!ethdev) > + return -ENODEV; This is not an error case, you can return success (0) here. Same applies to txgbe too. ^ permalink raw reply [flat|nested] 14+ messages in thread
* [dpdk-dev] [PATCH v4 4/6] net/ngbe: add device init and uninit 2021-04-06 9:30 [dpdk-dev] [PATCH v4 0/6] net: ngbe PMD Jiawen Wu ` (2 preceding siblings ...) 2021-04-06 9:30 ` [dpdk-dev] [PATCH v4 3/6] net/ngbe: support probe and remove Jiawen Wu @ 2021-04-06 9:30 ` Jiawen Wu 2021-04-06 9:30 ` [dpdk-dev] [PATCH v4 5/6] net/ngbe: add log type and error type Jiawen Wu ` (2 subsequent siblings) 6 siblings, 0 replies; 14+ messages in thread From: Jiawen Wu @ 2021-04-06 9:30 UTC (permalink / raw) To: dev; +Cc: Jiawen Wu Add basic init and uninit function. Map device IDs and subsystem IDs to single ID for easy operation. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> --- drivers/net/ngbe/base/meson.build | 4 +- drivers/net/ngbe/base/ngbe.h | 11 ++ drivers/net/ngbe/base/ngbe_hw.c | 59 ++++++++++ drivers/net/ngbe/base/ngbe_hw.h | 12 ++ drivers/net/ngbe/base/ngbe_osdep.h | 174 +++++++++++++++++++++++++++++ drivers/net/ngbe/base/ngbe_type.h | 27 +++++ drivers/net/ngbe/ngbe_ethdev.c | 36 +++++- drivers/net/ngbe/ngbe_ethdev.h | 7 ++ 8 files changed, 327 insertions(+), 3 deletions(-) create mode 100644 drivers/net/ngbe/base/ngbe.h create mode 100644 drivers/net/ngbe/base/ngbe_hw.c create mode 100644 drivers/net/ngbe/base/ngbe_hw.h create mode 100644 drivers/net/ngbe/base/ngbe_osdep.h create mode 100644 drivers/net/ngbe/base/ngbe_type.h diff --git a/drivers/net/ngbe/base/meson.build b/drivers/net/ngbe/base/meson.build index b4fc6a53b..d3616148f 100644 --- a/drivers/net/ngbe/base/meson.build +++ b/drivers/net/ngbe/base/meson.build @@ -1,7 +1,9 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2018-2020 -sources = [] +sources = [ + 'ngbe_hw.c', +] error_cflags = [] diff --git a/drivers/net/ngbe/base/ngbe.h b/drivers/net/ngbe/base/ngbe.h new file mode 100644 index 000000000..cdd435a0a --- /dev/null +++ b/drivers/net/ngbe/base/ngbe.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018-2020 + */ + +#ifndef _NGBE_H_ +#define _NGBE_H_ + +#include "ngbe_type.h" +#include "ngbe_hw.h" + +#endif /* _NGBE_H_ */ diff --git a/drivers/net/ngbe/base/ngbe_hw.c b/drivers/net/ngbe/base/ngbe_hw.c new file mode 100644 index 000000000..2a74405e3 --- /dev/null +++ b/drivers/net/ngbe/base/ngbe_hw.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018-2020 + */ + +#include "ngbe_hw.h" + +void ngbe_map_device_id(struct ngbe_hw *hw) +{ + u16 oem = hw->sub_system_id & NGBE_OEM_MASK; + u16 internal = hw->sub_system_id & NGBE_INTERNAL_MASK; + hw->is_pf = true; + + /* move subsystem_device_id to device_id */ + switch (hw->device_id) { + case NGBE_DEV_ID_EM_WX1860AL_W_VF: + case NGBE_DEV_ID_EM_WX1860A2_VF: + case NGBE_DEV_ID_EM_WX1860A2S_VF: + case NGBE_DEV_ID_EM_WX1860A4_VF: + case NGBE_DEV_ID_EM_WX1860A4S_VF: + case NGBE_DEV_ID_EM_WX1860AL2_VF: + case NGBE_DEV_ID_EM_WX1860AL2S_VF: + case NGBE_DEV_ID_EM_WX1860AL4_VF: + case NGBE_DEV_ID_EM_WX1860AL4S_VF: + case NGBE_DEV_ID_EM_WX1860NCSI_VF: + case NGBE_DEV_ID_EM_WX1860A1_VF: + case NGBE_DEV_ID_EM_WX1860A1L_VF: + hw->device_id = NGBE_DEV_ID_EM_VF; + hw->sub_device_id = NGBE_SUB_DEV_ID_EM_VF; + hw->is_pf = false; + break; + case NGBE_DEV_ID_EM_WX1860AL_W: + case NGBE_DEV_ID_EM_WX1860A2: + case NGBE_DEV_ID_EM_WX1860A2S: + case NGBE_DEV_ID_EM_WX1860A4: + case NGBE_DEV_ID_EM_WX1860A4S: + case NGBE_DEV_ID_EM_WX1860AL2: + case NGBE_DEV_ID_EM_WX1860AL2S: + case NGBE_DEV_ID_EM_WX1860AL4: + case NGBE_DEV_ID_EM_WX1860AL4S: + case NGBE_DEV_ID_EM_WX1860NCSI: + case NGBE_DEV_ID_EM_WX1860A1: + case NGBE_DEV_ID_EM_WX1860A1L: + hw->device_id = NGBE_DEV_ID_EM; + if (oem == NGBE_LY_M88E1512_SFP || + internal == NGBE_INTERNAL_SFP) + hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_SFP; + else if (hw->sub_system_id == NGBE_SUB_DEV_ID_EM_M88E1512_RJ45) + hw->sub_device_id = NGBE_SUB_DEV_ID_EM_MVL_RGMII; + else if (oem == NGBE_YT8521S_SFP || + oem == NGBE_LY_YT8521S_SFP) + hw->sub_device_id = NGBE_SUB_DEV_ID_EM_YT8521S_SFP; + else + hw->sub_device_id = NGBE_SUB_DEV_ID_EM_RTL_SGMII; + break; + default: + break; + } +} + diff --git a/drivers/net/ngbe/base/ngbe_hw.h b/drivers/net/ngbe/base/ngbe_hw.h new file mode 100644 index 000000000..0dba04a54 --- /dev/null +++ b/drivers/net/ngbe/base/ngbe_hw.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018-2020 + */ + +#ifndef _NGBE_HW_H_ +#define _NGBE_HW_H_ + +#include "ngbe_type.h" + +void ngbe_map_device_id(struct ngbe_hw *hw); + +#endif /* _NGBE_HW_H_ */ diff --git a/drivers/net/ngbe/base/ngbe_osdep.h b/drivers/net/ngbe/base/ngbe_osdep.h new file mode 100644 index 000000000..8a564fd14 --- /dev/null +++ b/drivers/net/ngbe/base/ngbe_osdep.h @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018-2020 + */ + +#ifndef _NGBE_OS_H_ +#define _NGBE_OS_H_ + +#include <string.h> +#include <stdint.h> +#include <stdio.h> +#include <stdarg.h> +#include <rte_version.h> +#include <rte_common.h> +#include <rte_debug.h> +#include <rte_cycles.h> +#include <rte_log.h> +#include <rte_byteorder.h> +#include <rte_config.h> +#include <rte_io.h> + +#define RTE_LIBRTE_NGBE_TM DCPV(1, 0) +#define TMZ_PADDR(mz) ((mz)->iova) +#define TMZ_VADDR(mz) ((mz)->addr) +#define TDEV_NAME(eth_dev) ((eth_dev)->device->name) + +#define ngbe_unused __rte_unused + +#define usec_delay(x) rte_delay_us(x) +#define msec_delay(x) rte_delay_ms(x) +#define usleep(x) rte_delay_us(x) +#define msleep(x) rte_delay_ms(x) + +#define FALSE 0 +#define TRUE 1 + +#ifndef false +#define false 0 +#endif +#ifndef true +#define true 1 +#endif +#define min(a, b) RTE_MIN(a, b) +#define max(a, b) RTE_MAX(a, b) + +/* Bunch of defines for shared code bogosity */ + +static inline void UNREFERENCED(const char *a __rte_unused, ...) {} +#define UNREFERENCED_PARAMETER(args...) UNREFERENCED("", ##args) + +#define STATIC static + +typedef uint8_t u8; +typedef int8_t s8; +typedef uint16_t u16; +typedef int16_t s16; +typedef uint32_t u32; +typedef int32_t s32; +typedef uint64_t u64; +typedef int64_t s64; + +/* Little Endian defines */ +#ifndef __le16 +#define __le16 u16 +#define __le32 u32 +#define __le64 u64 +#endif +#ifndef __be16 +#define __be16 u16 +#define __be32 u32 +#define __be64 u64 +#endif + +/* Bit shift and mask */ +#define BIT_MASK4 (0x0000000FU) +#define BIT_MASK8 (0x000000FFU) +#define BIT_MASK16 (0x0000FFFFU) +#define BIT_MASK32 (0xFFFFFFFFU) +#define BIT_MASK64 (0xFFFFFFFFFFFFFFFFUL) + +#ifndef cpu_to_le32 +#define cpu_to_le16(v) rte_cpu_to_le_16((u16)(v)) +#define cpu_to_le32(v) rte_cpu_to_le_32((u32)(v)) +#define cpu_to_le64(v) rte_cpu_to_le_64((u64)(v)) +#define le_to_cpu16(v) rte_le_to_cpu_16((u16)(v)) +#define le_to_cpu32(v) rte_le_to_cpu_32((u32)(v)) +#define le_to_cpu64(v) rte_le_to_cpu_64((u64)(v)) + +#define cpu_to_be16(v) rte_cpu_to_be_16((u16)(v)) +#define cpu_to_be32(v) rte_cpu_to_be_32((u32)(v)) +#define cpu_to_be64(v) rte_cpu_to_be_64((u64)(v)) +#define be_to_cpu16(v) rte_be_to_cpu_16((u16)(v)) +#define be_to_cpu32(v) rte_be_to_cpu_32((u32)(v)) +#define be_to_cpu64(v) rte_be_to_cpu_64((u64)(v)) + +#define le_to_be16(v) rte_bswap16((u16)(v)) +#define le_to_be32(v) rte_bswap32((u32)(v)) +#define le_to_be64(v) rte_bswap64((u64)(v)) +#define be_to_le16(v) rte_bswap16((u16)(v)) +#define be_to_le32(v) rte_bswap32((u32)(v)) +#define be_to_le64(v) rte_bswap64((u64)(v)) + +#define npu_to_le16(v) (v) +#define npu_to_le32(v) (v) +#define npu_to_le64(v) (v) +#define le_to_npu16(v) (v) +#define le_to_npu32(v) (v) +#define le_to_npu64(v) (v) + +#define npu_to_be16(v) le_to_be16((u16)(v)) +#define npu_to_be32(v) le_to_be32((u32)(v)) +#define npu_to_be64(v) le_to_be64((u64)(v)) +#define be_to_npu16(v) be_to_le16((u16)(v)) +#define be_to_npu32(v) be_to_le32((u32)(v)) +#define be_to_npu64(v) be_to_le64((u64)(v)) +#endif /* !cpu_to_le32 */ + +static inline u16 REVERT_BIT_MASK16(u16 mask) +{ + mask = ((mask & 0x5555) << 1) | ((mask & 0xAAAA) >> 1); + mask = ((mask & 0x3333) << 2) | ((mask & 0xCCCC) >> 2); + mask = ((mask & 0x0F0F) << 4) | ((mask & 0xF0F0) >> 4); + return ((mask & 0x00FF) << 8) | ((mask & 0xFF00) >> 8); +} + +static inline u32 REVERT_BIT_MASK32(u32 mask) +{ + mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1); + mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2); + mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4); + mask = ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8); + return ((mask & 0x0000FFFF) << 16) | ((mask & 0xFFFF0000) >> 16); +} + +static inline u64 REVERT_BIT_MASK64(u64 mask) +{ + mask = ((mask & 0x5555555555555555) << 1) | + ((mask & 0xAAAAAAAAAAAAAAAA) >> 1); + mask = ((mask & 0x3333333333333333) << 2) | + ((mask & 0xCCCCCCCCCCCCCCCC) >> 2); + mask = ((mask & 0x0F0F0F0F0F0F0F0F) << 4) | + ((mask & 0xF0F0F0F0F0F0F0F0) >> 4); + mask = ((mask & 0x00FF00FF00FF00FF) << 8) | + ((mask & 0xFF00FF00FF00FF00) >> 8); + mask = ((mask & 0x0000FFFF0000FFFF) << 16) | + ((mask & 0xFFFF0000FFFF0000) >> 16); + return ((mask & 0x00000000FFFFFFFF) << 32) | + ((mask & 0xFFFFFFFF00000000) >> 32); +} + +#define IOMEM + +#define prefetch(x) rte_prefetch0(x) + +#define ARRAY_SIZE(x) ((int32_t)RTE_DIM(x)) + +#ifndef MAX_UDELAY_MS +#define MAX_UDELAY_MS 5 +#endif + +#define ETH_ADDR_LEN 6 +#define ETH_FCS_LEN 4 + +/* Check whether address is multicast. This is little-endian specific check.*/ +#define NGBE_IS_MULTICAST(address) \ + rte_is_multicast_ether_addr(address) + +/* Check whether an address is broadcast. */ +#define NGBE_IS_BROADCAST(address) \ + rte_is_broadcast_ether_addr(address) + +#define ETH_P_8021Q 0x8100 +#define ETH_P_8021AD 0x88A8 + +#endif /* _NGBE_OS_H_ */ diff --git a/drivers/net/ngbe/base/ngbe_type.h b/drivers/net/ngbe/base/ngbe_type.h new file mode 100644 index 000000000..f143ecfd0 --- /dev/null +++ b/drivers/net/ngbe/base/ngbe_type.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018-2020 + */ + +#ifndef _NGBE_TYPE_H_ +#define _NGBE_TYPE_H_ + +#define NGBE_ALIGN 128 /* as intel did */ + +#include "ngbe_osdep.h" +#include "ngbe_devids.h" + +struct ngbe_hw { + void IOMEM *hw_addr; + u16 device_id; + u16 vendor_id; + u16 sub_device_id; + u16 sub_system_id; + bool allow_unsupported_sfp; + + uint64_t isb_dma; + void IOMEM *isb_mem; + + bool is_pf; +}; + +#endif /* _NGBE_TYPE_H_ */ diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c index d938fd68a..8c1accbbc 100644 --- a/drivers/net/ngbe/ngbe_ethdev.c +++ b/drivers/net/ngbe/ngbe_ethdev.c @@ -5,9 +5,11 @@ #include <rte_common.h> #include <ethdev_pci.h> -#include <base/ngbe_devids.h> +#include "base/ngbe.h" #include "ngbe_ethdev.h" +static int ngbe_dev_close(struct rte_eth_dev *dev); + /* * The set of PCI devices this driver supports */ @@ -31,12 +33,31 @@ static int eth_ngbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) { struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + struct ngbe_hw *hw = NGBE_DEV_HW(eth_dev); + const struct rte_memzone *mz; if (rte_eal_process_type() != RTE_PROC_PRIMARY) return 0; rte_eth_copy_pci_info(eth_dev, pci_dev); + /* Vendor and Device ID need to be set before init of shared code */ + hw->device_id = pci_dev->id.device_id; + hw->vendor_id = pci_dev->id.vendor_id; + hw->sub_system_id = pci_dev->id.subsystem_device_id; + ngbe_map_device_id(hw); + hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; + hw->allow_unsupported_sfp = 1; + + /* Reserve memory for interrupt status block */ + mz = rte_eth_dma_zone_reserve(eth_dev, "ngbe_driver", -1, + 16, NGBE_ALIGN, SOCKET_ID_ANY); + if (mz == NULL) + return -ENOMEM; + + hw->isb_dma = TMZ_PADDR(mz); + hw->isb_mem = TMZ_VADDR(mz); + return 0; } @@ -46,7 +67,7 @@ eth_ngbe_dev_uninit(struct rte_eth_dev *eth_dev) if (rte_eal_process_type() != RTE_PROC_PRIMARY) return 0; - RTE_SET_USED(eth_dev); + ngbe_dev_close(eth_dev); return 0; } @@ -102,6 +123,17 @@ static struct rte_pci_driver rte_ngbe_pmd = { .remove = eth_ngbe_pci_remove, }; +/* + * Reset and stop device. + */ +static int +ngbe_dev_close(struct rte_eth_dev *dev) +{ + RTE_SET_USED(dev); + + return 0; +} + RTE_PMD_REGISTER_PCI(net_ngbe, rte_ngbe_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_ngbe, pci_id_ngbe_map); RTE_PMD_REGISTER_KMOD_DEP(net_ngbe, "* igb_uio | uio_pci_generic | vfio-pci"); diff --git a/drivers/net/ngbe/ngbe_ethdev.h b/drivers/net/ngbe/ngbe_ethdev.h index 8dab39faf..613ba0eca 100644 --- a/drivers/net/ngbe/ngbe_ethdev.h +++ b/drivers/net/ngbe/ngbe_ethdev.h @@ -9,6 +9,13 @@ * Structure to store private data for each driver instance (for each port). */ struct ngbe_adapter { + struct ngbe_hw hw; }; +#define NGBE_DEV_ADAPTER(dev) \ + ((struct ngbe_adapter *)(dev)->data->dev_private) + +#define NGBE_DEV_HW(dev) \ + (&((struct ngbe_adapter *)(dev)->data->dev_private)->hw) + #endif /* _NGBE_ETHDEV_H_ */ -- 2.21.0.windows.1 ^ permalink raw reply [flat|nested] 14+ messages in thread
* [dpdk-dev] [PATCH v4 5/6] net/ngbe: add log type and error type 2021-04-06 9:30 [dpdk-dev] [PATCH v4 0/6] net: ngbe PMD Jiawen Wu ` (3 preceding siblings ...) 2021-04-06 9:30 ` [dpdk-dev] [PATCH v4 4/6] net/ngbe: add device init and uninit Jiawen Wu @ 2021-04-06 9:30 ` Jiawen Wu 2021-04-06 9:30 ` [dpdk-dev] [PATCH v4 6/6] net/ngbe: define registers Jiawen Wu 2021-04-09 14:47 ` [dpdk-dev] [PATCH v4 0/6] net: ngbe PMD Ferruh Yigit 6 siblings, 0 replies; 14+ messages in thread From: Jiawen Wu @ 2021-04-06 9:30 UTC (permalink / raw) To: dev; +Cc: Jiawen Wu Add log type and error type to trace functions. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> --- doc/guides/nics/ngbe.rst | 20 +++++ drivers/net/ngbe/base/ngbe_status.h | 124 ++++++++++++++++++++++++++++ drivers/net/ngbe/base/ngbe_type.h | 1 + drivers/net/ngbe/ngbe_ethdev.c | 16 ++++ drivers/net/ngbe/ngbe_logs.h | 45 ++++++++++ 5 files changed, 206 insertions(+) create mode 100644 drivers/net/ngbe/base/ngbe_status.h create mode 100644 drivers/net/ngbe/ngbe_logs.h diff --git a/doc/guides/nics/ngbe.rst b/doc/guides/nics/ngbe.rst index 007d8e80e..1be045f48 100644 --- a/doc/guides/nics/ngbe.rst +++ b/doc/guides/nics/ngbe.rst @@ -15,6 +15,26 @@ Prerequisites - Follow the DPDK :ref:`Getting Started Guide for Linux <linux_gsg>` to setup the basic DPDK environment. +Pre-Installation Configuration +------------------------------ + +Dynamic Logging Parameters +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +One may leverage EAL option "--log-level" to change default levels +for the log types supported by the driver. The option is used with +an argument typically consisting of two parts separated by a colon. + +NGBE PMD provides the following log types available for control: + +- ``pmd.net.ngbe.driver`` (default level is **notice**) + + Affects driver-wide messages unrelated to any particular devices. + +- ``pmd.net.ngbe.init`` (default level is **notice**) + + Extra logging of the messages during PMD initialization. + Driver compilation and testing ------------------------------ diff --git a/drivers/net/ngbe/base/ngbe_status.h b/drivers/net/ngbe/base/ngbe_status.h new file mode 100644 index 000000000..b2e7cfb29 --- /dev/null +++ b/drivers/net/ngbe/base/ngbe_status.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018-2020 + */ + +#ifndef _NGBE_STATUS_H_ +#define _NGBE_STATUS_H_ + +/* Error Codes: + * common error + * module error(simple) + * module error(detailed) + * + * (-256, 256): reserved for non-ngbe defined error code + */ +#define TERR_BASE (0x100) +enum ngbe_error { + TERR_NULL = TERR_BASE, + TERR_ANY, + TERR_NOSUPP, + TERR_NOIMPL, + TERR_NOMEM, + TERR_NOSPACE, + TERR_NOENTRY, + TERR_CONFIG, + TERR_ARGS, + TERR_PARAM, + TERR_INVALID, + TERR_TIMEOUT, + TERR_VERSION, + TERR_REGISTER, + TERR_FEATURE, + TERR_RESET, + TERR_AUTONEG, + TERR_MBX, + TERR_I2C, + TERR_FC, + TERR_FLASH, + TERR_DEVICE, + TERR_HOSTIF, + TERR_SRAM, + TERR_EEPROM, + TERR_EEPROM_CHECKSUM, + TERR_EEPROM_PROTECT, + TERR_EEPROM_VERSION, + TERR_MAC, + TERR_MAC_ADDR, + TERR_SFP, + TERR_SFP_INITSEQ, + TERR_SFP_PRESENT, + TERR_SFP_SUPPORT, + TERR_SFP_SETUP, + TERR_PHY, + TERR_PHY_ADDR, + TERR_PHY_INIT, + TERR_FDIR_CMD, + TERR_FDIR_REINIT, + TERR_SWFW_SYNC, + TERR_SWFW_COMMAND, + TERR_FC_CFG, + TERR_FC_NEGO, + TERR_LINK_SETUP, + TERR_PCIE_PENDING, + TERR_PBA_SECTION, + TERR_OVERTEMP, + TERR_UNDERTEMP, + TERR_XPCS_POWERUP, +}; + +/* WARNING: just for legacy compatibility */ +#define NGBE_NOT_IMPLEMENTED 0x7FFFFFFF +#define NGBE_ERR_OPS_DUMMY 0x3FFFFFFF + +/* Error Codes */ +#define NGBE_ERR_EEPROM -(TERR_BASE + 1) +#define NGBE_ERR_EEPROM_CHECKSUM -(TERR_BASE + 2) +#define NGBE_ERR_PHY -(TERR_BASE + 3) +#define NGBE_ERR_CONFIG -(TERR_BASE + 4) +#define NGBE_ERR_PARAM -(TERR_BASE + 5) +#define NGBE_ERR_MAC_TYPE -(TERR_BASE + 6) +#define NGBE_ERR_UNKNOWN_PHY -(TERR_BASE + 7) +#define NGBE_ERR_LINK_SETUP -(TERR_BASE + 8) +#define NGBE_ERR_ADAPTER_STOPPED -(TERR_BASE + 9) +#define NGBE_ERR_INVALID_MAC_ADDR -(TERR_BASE + 10) +#define NGBE_ERR_DEVICE_NOT_SUPPORTED -(TERR_BASE + 11) +#define NGBE_ERR_MASTER_REQUESTS_PENDING -(TERR_BASE + 12) +#define NGBE_ERR_INVALID_LINK_SETTINGS -(TERR_BASE + 13) +#define NGBE_ERR_AUTONEG_NOT_COMPLETE -(TERR_BASE + 14) +#define NGBE_ERR_RESET_FAILED -(TERR_BASE + 15) +#define NGBE_ERR_SWFW_SYNC -(TERR_BASE + 16) +#define NGBE_ERR_PHY_ADDR_INVALID -(TERR_BASE + 17) +#define NGBE_ERR_I2C -(TERR_BASE + 18) +#define NGBE_ERR_SFP_NOT_SUPPORTED -(TERR_BASE + 19) +#define NGBE_ERR_SFP_NOT_PRESENT -(TERR_BASE + 20) +#define NGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -(TERR_BASE + 21) +#define NGBE_ERR_NO_SAN_ADDR_PTR -(TERR_BASE + 22) +#define NGBE_ERR_FDIR_REINIT_FAILED -(TERR_BASE + 23) +#define NGBE_ERR_EEPROM_VERSION -(TERR_BASE + 24) +#define NGBE_ERR_NO_SPACE -(TERR_BASE + 25) +#define NGBE_ERR_OVERTEMP -(TERR_BASE + 26) +#define NGBE_ERR_FC_NOT_NEGOTIATED -(TERR_BASE + 27) +#define NGBE_ERR_FC_NOT_SUPPORTED -(TERR_BASE + 28) +#define NGBE_ERR_SFP_SETUP_NOT_COMPLETE -(TERR_BASE + 30) +#define NGBE_ERR_PBA_SECTION -(TERR_BASE + 31) +#define NGBE_ERR_INVALID_ARGUMENT -(TERR_BASE + 32) +#define NGBE_ERR_HOST_INTERFACE_COMMAND -(TERR_BASE + 33) +#define NGBE_ERR_OUT_OF_MEM -(TERR_BASE + 34) +#define NGBE_ERR_FEATURE_NOT_SUPPORTED -(TERR_BASE + 36) +#define NGBE_ERR_EEPROM_PROTECTED_REGION -(TERR_BASE + 37) +#define NGBE_ERR_FDIR_CMD_INCOMPLETE -(TERR_BASE + 38) +#define NGBE_ERR_FW_RESP_INVALID -(TERR_BASE + 39) +#define NGBE_ERR_TOKEN_RETRY -(TERR_BASE + 40) +#define NGBE_ERR_FLASH_LOADING_FAILED -(TERR_BASE + 41) + +#define NGBE_ERR_NOSUPP -(TERR_BASE + 42) +#define NGBE_ERR_UNDERTEMP -(TERR_BASE + 43) +#define NGBE_ERR_XPCS_POWER_UP_FAILED -(TERR_BASE + 44) +#define NGBE_ERR_PHY_INIT_NOT_DONE -(TERR_BASE + 45) +#define NGBE_ERR_TIMEOUT -(TERR_BASE + 46) +#define NGBE_ERR_REGISTER -(TERR_BASE + 47) +#define NGBE_ERR_MNG_ACCESS_FAILED -(TERR_BASE + 49) +#define NGBE_ERR_PHY_TYPE -(TERR_BASE + 50) +#define NGBE_ERR_PHY_TIMEOUT -(TERR_BASE + 51) + +#endif /* _NGBE_STATUS_H_ */ diff --git a/drivers/net/ngbe/base/ngbe_type.h b/drivers/net/ngbe/base/ngbe_type.h index f143ecfd0..30d66f109 100644 --- a/drivers/net/ngbe/base/ngbe_type.h +++ b/drivers/net/ngbe/base/ngbe_type.h @@ -7,6 +7,7 @@ #define NGBE_ALIGN 128 /* as intel did */ +#include "ngbe_status.h" #include "ngbe_osdep.h" #include "ngbe_devids.h" diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c index 8c1accbbc..4608b1063 100644 --- a/drivers/net/ngbe/ngbe_ethdev.c +++ b/drivers/net/ngbe/ngbe_ethdev.c @@ -5,6 +5,7 @@ #include <rte_common.h> #include <ethdev_pci.h> +#include "ngbe_logs.h" #include "base/ngbe.h" #include "ngbe_ethdev.h" @@ -36,6 +37,8 @@ eth_ngbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) struct ngbe_hw *hw = NGBE_DEV_HW(eth_dev); const struct rte_memzone *mz; + PMD_INIT_FUNC_TRACE(); + if (rte_eal_process_type() != RTE_PROC_PRIMARY) return 0; @@ -64,6 +67,8 @@ eth_ngbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) static int eth_ngbe_dev_uninit(struct rte_eth_dev *eth_dev) { + PMD_INIT_FUNC_TRACE(); + if (rte_eal_process_type() != RTE_PROC_PRIMARY) return 0; @@ -129,6 +134,8 @@ static struct rte_pci_driver rte_ngbe_pmd = { static int ngbe_dev_close(struct rte_eth_dev *dev) { + PMD_INIT_FUNC_TRACE(); + RTE_SET_USED(dev); return 0; @@ -138,3 +145,12 @@ RTE_PMD_REGISTER_PCI(net_ngbe, rte_ngbe_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_ngbe, pci_id_ngbe_map); RTE_PMD_REGISTER_KMOD_DEP(net_ngbe, "* igb_uio | uio_pci_generic | vfio-pci"); +RTE_LOG_REGISTER(ngbe_logtype_init, pmd.net.ngbe.init, NOTICE); +RTE_LOG_REGISTER(ngbe_logtype_driver, pmd.net.ngbe.driver, NOTICE); + +#ifdef RTE_ETHDEV_DEBUG_RX + RTE_LOG_REGISTER(ngbe_logtype_rx, pmd.net.ngbe.rx, DEBUG); +#endif +#ifdef RTE_ETHDEV_DEBUG_TX + RTE_LOG_REGISTER(ngbe_logtype_tx, pmd.net.ngbe.tx, DEBUG); +#endif diff --git a/drivers/net/ngbe/ngbe_logs.h b/drivers/net/ngbe/ngbe_logs.h new file mode 100644 index 000000000..c72095ae7 --- /dev/null +++ b/drivers/net/ngbe/ngbe_logs.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018-2020 + */ + +#ifndef _NGBE_LOGS_H_ +#define _NGBE_LOGS_H_ + +/* + * PMD_USER_LOG: for user + */ +extern int ngbe_logtype_init; +#define PMD_INIT_LOG(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, ngbe_logtype_init, \ + "%s(): " fmt "\n", __func__, ##args) + +extern int ngbe_logtype_driver; +#define PMD_DRV_LOG(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, ngbe_logtype_driver, \ + "%s(): " fmt "\n", __func__, ##args) + +#ifdef RTE_ETHDEV_DEBUG_RX +extern int ngbe_logtype_rx; +#define PMD_RX_LOG(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, ngbe_logtype_rx, \ + "%s(): " fmt "\n", __func__, ##args) +#else +#define PMD_RX_LOG(level, fmt, args...) do { } while (0) +#endif + +#ifdef RTE_ETHDEV_DEBUG_TX +extern int ngbe_logtype_tx; +#define PMD_TX_LOG(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, ngbe_logtype_tx, \ + "%s(): " fmt "\n", __func__, ##args) +#else +#define PMD_TX_LOG(level, fmt, args...) do { } while (0) +#endif + +#define TLOG_DEBUG(fmt, args...) PMD_DRV_LOG(DEBUG, fmt, ##args) + +#define DEBUGOUT(fmt, args...) TLOG_DEBUG(fmt, ##args) +#define PMD_INIT_FUNC_TRACE() TLOG_DEBUG(" >>") +#define DEBUGFUNC(fmt) TLOG_DEBUG(fmt) + +#endif /* _NGBE_LOGS_H_ */ -- 2.21.0.windows.1 ^ permalink raw reply [flat|nested] 14+ messages in thread
* [dpdk-dev] [PATCH v4 6/6] net/ngbe: define registers 2021-04-06 9:30 [dpdk-dev] [PATCH v4 0/6] net: ngbe PMD Jiawen Wu ` (4 preceding siblings ...) 2021-04-06 9:30 ` [dpdk-dev] [PATCH v4 5/6] net/ngbe: add log type and error type Jiawen Wu @ 2021-04-06 9:30 ` Jiawen Wu 2021-04-09 14:47 ` [dpdk-dev] [PATCH v4 0/6] net: ngbe PMD Ferruh Yigit 6 siblings, 0 replies; 14+ messages in thread From: Jiawen Wu @ 2021-04-06 9:30 UTC (permalink / raw) To: dev; +Cc: Jiawen Wu Define all registers that will be used. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> --- drivers/net/ngbe/base/ngbe_regs.h | 1489 +++++++++++++++++++++++++++++ drivers/net/ngbe/base/ngbe_type.h | 2 + 2 files changed, 1491 insertions(+) create mode 100644 drivers/net/ngbe/base/ngbe_regs.h diff --git a/drivers/net/ngbe/base/ngbe_regs.h b/drivers/net/ngbe/base/ngbe_regs.h new file mode 100644 index 000000000..dacb5c186 --- /dev/null +++ b/drivers/net/ngbe/base/ngbe_regs.h @@ -0,0 +1,1489 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018-2020 + */ + +#ifndef _NGBE_REGS_H_ +#define _NGBE_REGS_H_ + +#define NGBE_PVMBX_QSIZE (16) /* 16*4B */ +#define NGBE_PVMBX_BSIZE (NGBE_PVMBX_QSIZE * 4) + +#define NGBE_REMOVED(a) (0) + +#define NGBE_REG_DUMMY 0xFFFFFF + +#define MS8(shift, mask) (((u8)(mask)) << (shift)) +#define LS8(val, shift, mask) (((u8)(val) & (u8)(mask)) << (shift)) +#define RS8(reg, shift, mask) (((u8)(reg) >> (shift)) & (u8)(mask)) + +#define MS16(shift, mask) (((u16)(mask)) << (shift)) +#define LS16(val, shift, mask) (((u16)(val) & (u16)(mask)) << (shift)) +#define RS16(reg, shift, mask) (((u16)(reg) >> (shift)) & (u16)(mask)) + +#define MS32(shift, mask) (((u32)(mask)) << (shift)) +#define LS32(val, shift, mask) (((u32)(val) & (u32)(mask)) << (shift)) +#define RS32(reg, shift, mask) (((u32)(reg) >> (shift)) & (u32)(mask)) + +#define MS64(shift, mask) (((u64)(mask)) << (shift)) +#define LS64(val, shift, mask) (((u64)(val) & (u64)(mask)) << (shift)) +#define RS64(reg, shift, mask) (((u64)(reg) >> (shift)) & (u64)(mask)) + +#define MS(shift, mask) MS32(shift, mask) +#define LS(val, shift, mask) LS32(val, shift, mask) +#define RS(reg, shift, mask) RS32(reg, shift, mask) + +#define ROUND_UP(x, y) (((x) + (y) - 1) / (y) * (y)) +#define ROUND_DOWN(x, y) ((x) / (y) * (y)) +#define ROUND_OVER(x, maxbits, unitbits) \ + ((x) >= 1 << (maxbits) ? 0 : (x) >> (unitbits)) + +/* autoc bits definition */ +#define NGBE_AUTOC NGBE_REG_DUMMY +#define NGBE_AUTOC_FLU MS64(0, 0x1) +#define NGBE_AUTOC_10G_PMA_PMD_MASK MS64(7, 0x3) /* parallel */ +#define NGBE_AUTOC_10G_XAUI LS64(0, 7, 0x3) +#define NGBE_AUTOC_10G_KX4 LS64(1, 7, 0x3) +#define NGBE_AUTOC_10G_CX4 LS64(2, 7, 0x3) +#define NGBE_AUTOC_10G_KR LS64(3, 7, 0x3) /* fixme */ +#define NGBE_AUTOC_1G_PMA_PMD_MASK MS64(9, 0x7) +#define NGBE_AUTOC_1G_BX LS64(0, 9, 0x7) +#define NGBE_AUTOC_1G_KX LS64(1, 9, 0x7) +#define NGBE_AUTOC_1G_SFI LS64(0, 9, 0x7) +#define NGBE_AUTOC_1G_KX_BX LS64(1, 9, 0x7) +#define NGBE_AUTOC_AN_RESTART MS64(12, 0x1) +#define NGBE_AUTOC_LMS_MASK MS64(13, 0x7) +#define NGBE_AUTOC_LMS_10G LS64(3, 13, 0x7) +#define NGBE_AUTOC_LMS_KX4_KX_KR LS64(4, 13, 0x7) +#define NGBE_AUTOC_LMS_SGMII_1G_100M LS64(5, 13, 0x7) +#define NGBE_AUTOC_LMS_KX4_KX_KR_1G_AN LS64(6, 13, 0x7) +#define NGBE_AUTOC_LMS_KX4_KX_KR_SGMII LS64(7, 13, 0x7) +#define NGBE_AUTOC_LMS_1G_LINK_NO_AN LS64(0, 13, 0x7) +#define NGBE_AUTOC_LMS_10G_LINK_NO_AN LS64(1, 13, 0x7) +#define NGBE_AUTOC_LMS_1G_AN LS64(2, 13, 0x7) +#define NGBE_AUTOC_LMS_KX4_AN LS64(4, 13, 0x7) +#define NGBE_AUTOC_LMS_KX4_AN_1G_AN LS64(6, 13, 0x7) +#define NGBE_AUTOC_LMS_ATTACH_TYPE LS64(7, 13, 0x7) +#define NGBE_AUTOC_LMS_AN MS64(15, 0x7) + +#define NGBE_AUTOC_KR_SUPP MS64(16, 0x1) +#define NGBE_AUTOC_FECR MS64(17, 0x1) +#define NGBE_AUTOC_FECA MS64(18, 0x1) +#define NGBE_AUTOC_AN_RX_ALIGN MS64(18, 0x1F) /* fixme */ +#define NGBE_AUTOC_AN_RX_DRIFT MS64(23, 0x3) +#define NGBE_AUTOC_AN_RX_LOOSE MS64(24, 0x3) +#define NGBE_AUTOC_PD_TMR MS64(25, 0x3) +#define NGBE_AUTOC_RF MS64(27, 0x1) +#define NGBE_AUTOC_ASM_PAUSE MS64(29, 0x1) +#define NGBE_AUTOC_SYM_PAUSE MS64(28, 0x1) +#define NGBE_AUTOC_PAUSE MS64(28, 0x3) +#define NGBE_AUTOC_KX_SUPP MS64(30, 0x1) +#define NGBE_AUTOC_KX4_SUPP MS64(31, 0x1) + +#define NGBE_AUTOC_10GS_PMA_PMD_MASK MS64(48, 0x3) /* serial */ +#define NGBE_AUTOC_10GS_KR LS64(0, 48, 0x3) +#define NGBE_AUTOC_10GS_XFI LS64(1, 48, 0x3) +#define NGBE_AUTOC_10GS_SFI LS64(2, 48, 0x3) +#define NGBE_AUTOC_LINK_DIA_MASK MS64(60, 0x7) +#define NGBE_AUTOC_LINK_DIA_D3_MASK LS64(5, 60, 0x7) + +#define NGBE_AUTOC_SPEED_MASK MS64(32, 0xFFFF) +#define NGBD_AUTOC_SPEED(r) RS64(r, 32, 0xFFFF) +#define NGBE_AUTOC_SPEED(v) LS64(v, 32, 0xFFFF) +#define NGBE_LINK_SPEED_UNKNOWN 0 +#define NGBE_LINK_SPEED_10M_FULL 0x0002 +#define NGBE_LINK_SPEED_100M_FULL 0x0008 +#define NGBE_LINK_SPEED_1GB_FULL 0x0020 +#define NGBE_LINK_SPEED_2_5GB_FULL 0x0400 +#define NGBE_LINK_SPEED_5GB_FULL 0x0800 +#define NGBE_LINK_SPEED_10GB_FULL 0x0080 +#define NGBE_LINK_SPEED_40GB_FULL 0x0100 +#define NGBE_AUTOC_AUTONEG MS64(63, 0x1) + + + +/* Hardware Datapath: + * RX: / Queue <- Filter \ + * Host | TC <=> SEC <=> MAC <=> PHY + * TX: \ Queue -> Filter / + * + * Packet Filter: + * RX: RSS < FDIR < Filter < Encrypt + * + * Macro Argument Naming: + * rp = ring pair [0,127] + * tc = traffic class [0,7] + * up = user priority [0,7] + * pi = pool index [0,63] + * r = register + * v = value + * s = shift + * m = mask + * i,j,k = array index + * H,L = high/low bits + * HI,LO = high/low state + */ + +#define NGBE_ETHPHYIF NGBE_REG_DUMMY +#define NGBE_ETHPHYIF_MDIO_ACT MS(1, 0x1) +#define NGBE_ETHPHYIF_MDIO_MODE MS(2, 0x1) +#define NGBE_ETHPHYIF_MDIO_BASE(r) RS(r, 3, 0x1F) +#define NGBE_ETHPHYIF_MDIO_SHARED MS(13, 0x1) +#define NGBE_ETHPHYIF_SPEED_10M MS(17, 0x1) +#define NGBE_ETHPHYIF_SPEED_100M MS(18, 0x1) +#define NGBE_ETHPHYIF_SPEED_1G MS(19, 0x1) +#define NGBE_ETHPHYIF_SPEED_2_5G MS(20, 0x1) +#define NGBE_ETHPHYIF_SPEED_10G MS(21, 0x1) +#define NGBE_ETHPHYIF_SGMII_ENABLE MS(25, 0x1) +#define NGBE_ETHPHYIF_INT_PHY_MODE MS(24, 0x1) +#define NGBE_ETHPHYIF_IO_XPCS MS(30, 0x1) +#define NGBE_ETHPHYIF_IO_EPHY MS(31, 0x1) + +/****************************************************************************** + * Chip Registers + ******************************************************************************/ +/** + * Chip Status + **/ +#define NGBE_PWR 0x010000 +#define NGBE_PWR_LAN(r) RS(r, 28, 0xC) +#define NGBE_PWR_LAN_0 (1) +#define NGBE_PWR_LAN_1 (2) +#define NGBE_PWR_LAN_2 (3) +#define NGBE_PWR_LAN_3 (4) +#define NGBE_CTL 0x010004 +#define NGBE_LOCKPF 0x010008 +#define NGBE_RST 0x01000C +#define NGBE_RST_SW MS(0, 0x1) +#define NGBE_RST_LAN(i) MS(((i) + 1), 0x1) +#define NGBE_RST_FW MS(5, 0x1) +#define NGBE_RST_ETH(i) MS(((i) + 29), 0x1) +#define NGBE_RST_GLB MS(31, 0x1) +#define NGBE_RST_DEFAULT (NGBE_RST_SW | \ + NGBE_RST_LAN(0) | \ + NGBE_RST_LAN(1) | \ + NGBE_RST_LAN(2) | \ + NGBE_RST_LAN(3)) +#define NGBE_PROB 0x010010 +#define NGBE_IODRV 0x010024 +#define NGBE_STAT 0x010028 +#define NGBE_STAT_MNGINIT MS(0, 0x1) +#define NGBE_STAT_MNGVETO MS(8, 0x1) +#define NGBE_STAT_ECCLAN0 MS(16, 0x1) +#define NGBE_STAT_ECCLAN1 MS(17, 0x1) +#define NGBE_STAT_ECCLAN2 MS(18, 0x1) +#define NGBE_STAT_ECCLAN3 MS(19, 0x1) +#define NGBE_STAT_ECCMNG MS(20, 0x1) +#define NGBE_STAT_ECCPCORE MS(21, 0X1) +#define NGBE_STAT_ECCPCIW MS(22, 0x1) +#define NGBE_STAT_ECCPCIEPHY MS(23, 0x1) +#define NGBE_STAT_ECCFMGR MS(24, 0x1) +#define NGBE_STAT_GPHY_IN_RST(i) MS(((i) + 9), 0x1) +#define NGBE_RSTSTAT 0x010030 +#define NGBE_RSTSTAT_PROG MS(20, 0x1) +#define NGBE_RSTSTAT_PREP MS(19, 0x1) +#define NGBE_RSTSTAT_TYPE_MASK MS(16, 0x7) +#define NGBE_RSTSTAT_TYPE(r) RS(r, 16, 0x7) +#define NGBE_RSTSTAT_TYPE_PE LS(0, 16, 0x7) +#define NGBE_RSTSTAT_TYPE_PWR LS(1, 16, 0x7) +#define NGBE_RSTSTAT_TYPE_HOT LS(2, 16, 0x7) +#define NGBE_RSTSTAT_TYPE_SW LS(3, 16, 0x7) +#define NGBE_RSTSTAT_TYPE_FW LS(4, 16, 0x7) +#define NGBE_RSTSTAT_TMRINIT_MASK MS(8, 0xFF) +#define NGBE_RSTSTAT_TMRINIT(v) LS(v, 8, 0xFF) +#define NGBE_RSTSTAT_TMRCNT_MASK MS(0, 0xFF) +#define NGBE_RSTSTAT_TMRCNT(v) LS(v, 0, 0xFF) +#define NGBE_PWRTMR 0x010034 + +/** + * SPI(Flash) + **/ +#define NGBE_SPICMD 0x010104 +#define NGBE_SPICMD_ADDR(v) LS(v, 0, 0xFFFFFF) +#define NGBE_SPICMD_CLK(v) LS(v, 25, 0x7) +#define NGBE_SPICMD_CMD(v) LS(v, 28, 0x7) +#define NGBE_SPIDAT 0x010108 +#define NGBE_SPIDAT_BYPASS MS(31, 0x1) +#define NGBE_SPIDAT_STATUS(v) LS(v, 16, 0xFF) +#define NGBE_SPIDAT_OPDONE MS(0, 0x1) +#define NGBE_SPISTAT 0x01010C +#define NGBE_SPISTAT_OPDONE MS(0, 0x1) +#define NGBE_SPISTAT_BPFLASH MS(31, 0x1) +#define NGBE_SPIUSRCMD 0x010110 +#define NGBE_SPICFG0 0x010114 +#define NGBE_SPICFG1 0x010118 + +/* FMGR Registers */ +#define NGBE_ILDRSTAT 0x010120 +#define NGBE_ILDRSTAT_PCIRST MS(0, 0x1) +#define NGBE_ILDRSTAT_PWRRST MS(1, 0x1) +#define NGBE_ILDRSTAT_SWRST MS(11, 0x1) +#define NGBE_ILDRSTAT_SWRST_LAN0 MS(13, 0x1) +#define NGBE_ILDRSTAT_SWRST_LAN1 MS(14, 0x1) +#define NGBE_ILDRSTAT_SWRST_LAN2 MS(15, 0x1) +#define NGBE_ILDRSTAT_SWRST_LAN3 MS(16, 0x1) + +#define NGBE_SRAM 0x010124 +#define NGBE_SRAM_SZ(v) LS(v, 28, 0x7) +#define NGBE_SRAMCTLECC 0x010130 +#define NGBE_SRAMINJECC 0x010134 +#define NGBE_SRAMECC 0x010138 + +/* Sensors for PVT(Process Voltage Temperature) */ +#define NGBE_TSCTRL 0x010300 +#define NGBE_TSCTRL_EVALMD MS(31, 0x1) +#define NGBE_TSEN 0x010304 +#define NGBE_TSEN_ENA MS(0, 0x1) +#define NGBE_TSSTAT 0x010308 +#define NGBE_TSSTAT_VLD MS(16, 0x1) +#define NGBE_TSSTAT_DATA(r) RS(r, 0, 0x3FF) +#define NGBE_TSATHRE 0x01030C +#define NGBE_TSDTHRE 0x010310 +#define NGBE_TSINTR 0x010314 +#define NGBE_TSINTR_AEN MS(0, 0x1) +#define NGBE_TSINTR_DEN MS(1, 0x1) +#define NGBE_TSALM 0x010318 +#define NGBE_TSALM_LO MS(0, 0x1) +#define NGBE_TSALM_HI MS(1, 0x1) + +#define NGBE_EFUSE_WDATA0 0x010320 +#define NGBE_EFUSE_WDATA1 0x010324 +#define NGBE_EFUSE_RDATA0 0x010328 +#define NGBE_EFUSE_RDATA1 0x01032C +#define NGBE_EFUSE_STATUS 0x010330 + +/****************************************************************************** + * Port Registers + ******************************************************************************/ +/* Internal PHY reg_offset [0,31] */ +#define NGBE_PHY_CONFIG(reg_offset) (0x014000 + (reg_offset) * 4) + +/* Port Control */ +#define NGBE_PORTCTL 0x014400 +#define NGBE_PORTCTL_VLANEXT MS(0, 0x1) +#define NGBE_PORTCTL_ETAG MS(1, 0x1) +#define NGBE_PORTCTL_QINQ MS(2, 0x1) +#define NGBE_PORTCTL_DRVLOAD MS(3, 0x1) +#define NGBE_PORTCTL_NUMVT_MASK MS(12, 0x1) +#define NGBE_PORTCTL_NUMVT_8 LS(1, 12, 0x1) +#define NGBE_PORTCTL_RSTDONE MS(14, 0x1) +#define NGBE_PORTCTL_TEREDODIA MS(27, 0x1) +#define NGBE_PORTCTL_GENEVEDIA MS(28, 0x1) +#define NGBE_PORTCTL_VXLANGPEDIA MS(30, 0x1) +#define NGBE_PORTCTL_VXLANDIA MS(31, 0x1) + +/* Port Status */ +#define NGBE_PORTSTAT 0x014404 +#define NGBE_PORTSTAT_BW_MASK MS(1, 0x7) +#define NGBE_PORTSTAT_BW_1G MS(1, 0x1) +#define NGBE_PORTSTAT_BW_100M MS(2, 0x1) +#define NGBE_PORTSTAT_BW_10M MS(3, 0x1) +#define NGBE_PORTSTAT_ID(r) RS(r, 8, 0x3) + +#define NGBE_EXTAG 0x014408 +#define NGBE_EXTAG_ETAG_MASK MS(0, 0xFFFF) +#define NGBE_EXTAG_ETAG(v) LS(v, 0, 0xFFFF) +#define NGBE_EXTAG_VLAN_MASK MS(16, 0xFFFF) +#define NGBE_EXTAG_VLAN(v) LS(v, 16, 0xFFFF) + +#define NGBE_TCPTIME 0x014420 + +#define NGBE_LEDCTL 0x014424 +#define NGBE_LEDCTL_SEL(s) MS((s), 0x1) +#define NGBE_LEDCTL_OD(s) MS(((s) + 16), 0x1) + /* s=1G(1),100M(2),10M(3) */ +#define NGBE_LEDCTL_100M (NGBE_LEDCTL_SEL(2) | NGBE_LEDCTL_OD(2)) + +#define NGBE_TAGTPID(i) (0x014430 + (i) * 4) /*0-3*/ +#define NGBE_TAGTPID_LSB_MASK MS(0, 0xFFFF) +#define NGBE_TAGTPID_LSB(v) LS(v, 0, 0xFFFF) +#define NGBE_TAGTPID_MSB_MASK MS(16, 0xFFFF) +#define NGBE_TAGTPID_MSB(v) LS(v, 16, 0xFFFF) + +#define NGBE_LAN_SPEED 0x014440 +#define NGBE_LAN_SPEED_MASK MS(0, 0x3) + +/* GPIO Registers */ +#define NGBE_GPIODATA 0x014800 +#define NGBE_GPIOBIT_0 MS(0, 0x1) /* O:tx fault */ +#define NGBE_GPIOBIT_1 MS(1, 0x1) /* O:tx disabled */ +#define NGBE_GPIOBIT_2 MS(2, 0x1) /* I:sfp module absent */ +#define NGBE_GPIOBIT_3 MS(3, 0x1) /* I:rx signal lost */ +#define NGBE_GPIOBIT_4 MS(4, 0x1) /* O:rate select, 1G(0) 10G(1) */ +#define NGBE_GPIOBIT_5 MS(5, 0x1) /* O:rate select, 1G(0) 10G(1) */ +#define NGBE_GPIOBIT_6 MS(6, 0x1) /* I:ext phy interrupt */ +#define NGBE_GPIOBIT_7 MS(7, 0x1) /* I:fan speed alarm */ +#define NGBE_GPIODIR 0x014804 +#define NGBE_GPIODIR_DDR(v) LS(v, 0, 0x3) +#define NGBE_GPIOCTL 0x014808 +#define NGBE_GPIOINTEN 0x014830 +#define NGBE_GPIOINTEN_INT(v) LS(v, 0, 0x3) +#define NGBE_GPIOINTMASK 0x014834 +#define NGBE_GPIOINTTYPE 0x014838 +#define NGBE_GPIOINTTYPE_LEVEL(v) LS(v, 0, 0x3) +#define NGBE_GPIOINTPOL 0x01483C +#define NGBE_GPIOINTPOL_ACT(v) LS(v, 0, 0x3) +#define NGBE_GPIOINTSTAT 0x014840 +#define NGBE_GPIOINTDB 0x014848 +#define NGBE_GPIOEOI 0x01484C +#define NGBE_GPIODAT 0x014850 + +/* TPH */ +#define NGBE_TPHCFG 0x014F00 + +/****************************************************************************** + * Transmit DMA Registers + ******************************************************************************/ +/* TDMA Control */ +#define NGBE_DMATXCTRL 0x018000 +#define NGBE_DMATXCTRL_ENA MS(0, 0x1) +#define NGBE_DMATXCTRL_TPID_MASK MS(16, 0xFFFF) +#define NGBE_DMATXCTRL_TPID(v) LS(v, 16, 0xFFFF) +#define NGBE_POOLTXENA(i) (0x018004 + (i) * 4) /*0*/ +#define NGBE_PRBTXDMACTL 0x018010 +#define NGBE_ECCTXDMACTL 0x018014 +#define NGBE_ECCTXDMAINJ 0x018018 +#define NGBE_ECCTXDMA 0x01801C +#define NGBE_PBTXDMATH 0x018020 +#define NGBE_QPTXLLI 0x018040 +#define NGBE_POOLTXLBET 0x018050 +#define NGBE_POOLTXASET 0x018058 +#define NGBE_POOLTXASMAC 0x018060 +#define NGBE_POOLTXASVLAN 0x018070 +#define NGBE_POOLTXDSA 0x0180A0 +#define NGBE_POOLTAG(pl) (0x018100 + (pl) * 4) /*0-7*/ +#define NGBE_POOLTAG_VTAG(v) LS(v, 0, 0xFFFF) +#define NGBE_POOLTAG_VTAG_MASK MS(0, 0xFFFF) +#define TXGBD_POOLTAG_VTAG_UP(r) RS(r, 13, 0x7) +#define NGBE_POOLTAG_TPIDSEL(v) LS(v, 24, 0x7) +#define NGBE_POOLTAG_ETAG_MASK MS(27, 0x3) +#define NGBE_POOLTAG_ETAG LS(2, 27, 0x3) +#define NGBE_POOLTAG_ACT_MASK MS(30, 0x3) +#define NGBE_POOLTAG_ACT_ALWAYS LS(1, 30, 0x3) +#define NGBE_POOLTAG_ACT_NEVER LS(2, 30, 0x3) + +/* Queue Arbiter(QoS) */ +#define NGBE_QARBTXCTL 0x018200 +#define NGBE_QARBTXCTL_DA MS(6, 0x1) +#define NGBE_QARBTXRATE 0x018404 +#define NGBE_QARBTXRATE_MIN(v) LS(v, 0, 0x3FFF) +#define NGBE_QARBTXRATE_MAX(v) LS(v, 16, 0x3FFF) + +/* ETAG */ +#define NGBE_POOLETAG(pl) (0x018700 + (pl) * 4) + +/****************************************************************************** + * Receive DMA Registers + ******************************************************************************/ +/* Receive Control */ +#define NGBE_ARBRXCTL 0x012000 +#define NGBE_ARBRXCTL_DIA MS(6, 0x1) +#define NGBE_POOLRXENA(i) (0x012004 + (i) * 4) /*0*/ +#define NGBE_PRBRDMA 0x012010 +#define NGBE_ECCRXDMACTL 0x012014 +#define NGBE_ECCRXDMAINJ 0x012018 +#define NGBE_ECCRXDMA 0x01201C +#define NGBE_POOLRXDNA 0x0120A0 +#define NGBE_QPRXDROP 0x012080 +#define NGBE_QPRXSTRPVLAN 0x012090 + +/****************************************************************************** + * Packet Buffer + ******************************************************************************/ +/* Flow Control */ +#define NGBE_FCXOFFTM 0x019200 +#define NGBE_FCWTRLO 0x019220 +#define NGBE_FCWTRLO_TH(v) LS(v, 10, 0x1FF) /*KB*/ +#define NGBE_FCWTRLO_XON MS(31, 0x1) +#define NGBE_FCWTRHI 0x019260 +#define NGBE_FCWTRHI_TH(v) LS(v, 10, 0x1FF) /*KB*/ +#define NGBE_FCWTRHI_XOFF MS(31, 0x1) +#define NGBE_RXFCRFSH 0x0192A0 +#define NGBE_RXFCFSH_TIME(v) LS(v, 0, 0xFFFF) +#define NGBE_FCSTAT 0x01CE00 +#define NGBE_FCSTAT_DLNK MS(0, 0x1) +#define NGBE_FCSTAT_ULNK MS(8, 0x1) + +#define NGBE_RXFCCFG 0x011090 +#define NGBE_RXFCCFG_FC MS(0, 0x1) +#define NGBE_TXFCCFG 0x0192A4 +#define NGBE_TXFCCFG_FC MS(3, 0x1) + +/* Data Buffer */ +#define NGBE_PBRXCTL 0x019000 +#define NGBE_PBRXCTL_ST MS(0, 0x1) +#define NGBE_PBRXCTL_ENA MS(31, 0x1) +#define NGBE_PBRXSTAT 0x019004 +#define NGBE_PBRXSIZE 0x019020 +#define NGBE_PBRXSIZE_KB(v) LS(v, 10, 0x3F) + +#define NGBE_PBRXOFTMR 0x019094 +#define NGBE_PBRXDBGCMD 0x019090 +#define NGBE_PBRXDBGDAT 0x0190A0 + +#define NGBE_PBTXSIZE 0x01CC00 + +/* LLI */ +#define NGBE_PBRXLLI 0x19080 +#define NGBE_PBRXLLI_SZLT(v) LS(v, 0, 0xFFF) +#define NGBE_PBRXLLI_UPLT(v) LS(v, 16, 0x7) +#define NGBE_PBRXLLI_UPEA MS(19, 0x1) + +/* Port Arbiter(QoS) */ +#define NGBE_PARBTXCTL 0x01CD00 +#define NGBE_PARBTXCTL_DA MS(6, 0x1) + +/****************************************************************************** + * Packet Filter (L2-7) + ******************************************************************************/ +/** + * Receive Scaling + **/ +#define NGBE_POOLRSS(pl) (0x019300 + (pl) * 4) /*0-7*/ +#define NGBE_POOLRSS_L4HDR MS(1, 0x1) +#define NGBE_POOLRSS_L3HDR MS(2, 0x1) +#define NGBE_POOLRSS_L2HDR MS(3, 0x1) +#define NGBE_POOLRSS_L2TUN MS(4, 0x1) +#define NGBE_POOLRSS_TUNHDR MS(5, 0x1) +#define NGBE_RSSTBL(i) (0x019400 + (i) * 4) /*32*/ +#define NGBE_RSSKEY(i) (0x019480 + (i) * 4) /*10*/ +#define NGBE_RACTL 0x0194F4 +#define NGBE_RACTL_RSSENA MS(2, 0x1) +#define NGBE_RACTL_RSSMASK MS(16, 0xFFFF) +#define NGBE_RACTL_RSSIPV4TCP MS(16, 0x1) +#define NGBE_RACTL_RSSIPV4 MS(17, 0x1) +#define NGBE_RACTL_RSSIPV6 MS(20, 0x1) +#define NGBE_RACTL_RSSIPV6TCP MS(21, 0x1) +#define NGBE_RACTL_RSSIPV4UDP MS(22, 0x1) +#define NGBE_RACTL_RSSIPV6UDP MS(23, 0x1) + +/** + * Flow Director + **/ +#define PERFECT_BUCKET_64KB_HASH_MASK 0x07FF /* 11 bits */ +#define PERFECT_BUCKET_128KB_HASH_MASK 0x0FFF /* 12 bits */ +#define PERFECT_BUCKET_256KB_HASH_MASK 0x1FFF /* 13 bits */ +#define SIG_BUCKET_64KB_HASH_MASK 0x1FFF /* 13 bits */ +#define SIG_BUCKET_128KB_HASH_MASK 0x3FFF /* 14 bits */ +#define SIG_BUCKET_256KB_HASH_MASK 0x7FFF /* 15 bits */ + +/** + * 5-tuple Filter + **/ +#define NGBE_5TFPORT(i) (0x019A00 + (i) * 4) /*0-7*/ +#define NGBE_5TFPORT_SRC(v) LS(v, 0, 0xFFFF) +#define NGBE_5TFPORT_DST(v) LS(v, 16, 0xFFFF) +#define NGBE_5TFCTL0(i) (0x019C00 + (i) * 4) /*0-7*/ +#define NGBE_5TFCTL0_PROTO(v) LS(v, 0, 0x3) +enum ngbe_5tuple_protocol { + NGBE_5TF_PROT_TCP = 0, + NGBE_5TF_PROT_UDP, + NGBE_5TF_PROT_SCTP, + NGBE_5TF_PROT_NONE, +}; +#define NGBE_5TFCTL0_PRI(v) LS(v, 2, 0x7) +#define NGBE_5TFCTL0_POOL(v) LS(v, 8, 0x7) +#define NGBE_5TFCTL0_MASK MS(27, 0xF) +#define NGBE_5TFCTL0_MSPORT MS(27, 0x1) +#define NGBE_5TFCTL0_MDPORT MS(28, 0x1) +#define NGBE_5TFCTL0_MPROTO MS(29, 0x1) +#define NGBE_5TFCTL0_MPOOL MS(30, 0x1) +#define NGBE_5TFCTL0_ENA MS(31, 0x1) +#define NGBE_5TFCTL1(i) (0x019E00 + (i) * 4) /*0-7*/ +#define NGBE_5TFCTL1_CHKSZ MS(12, 0x1) +#define NGBE_5TFCTL1_LLI MS(20, 0x1) +#define NGBE_5TFCTL1_QP(v) LS(v, 21, 0x7) + +/** + * Storm Control + **/ +#define NGBE_STRMCTL 0x015004 +#define NGBE_STRMCTL_MCPNSH MS(0, 0x1) +#define NGBE_STRMCTL_MCDROP MS(1, 0x1) +#define NGBE_STRMCTL_BCPNSH MS(2, 0x1) +#define NGBE_STRMCTL_BCDROP MS(3, 0x1) +#define NGBE_STRMCTL_DFTPOOL MS(4, 0x1) +#define NGBE_STRMCTL_ITVL(v) LS(v, 8, 0x3FF) +#define NGBE_STRMTH 0x015008 +#define NGBE_STRMTH_MC(v) LS(v, 0, 0xFFFF) +#define NGBE_STRMTH_BC(v) LS(v, 16, 0xFFFF) + +/****************************************************************************** + * Ether Flow + ******************************************************************************/ +#define NGBE_PSRCTL 0x015000 +#define NGBE_PSRCTL_TPE MS(4, 0x1) +#define NGBE_PSRCTL_ADHF12_MASK MS(5, 0x3) +#define NGBE_PSRCTL_ADHF12(v) LS(v, 5, 0x3) +#define NGBE_PSRCTL_UCHFENA MS(7, 0x1) +#define NGBE_PSRCTL_MCHFENA MS(7, 0x1) +#define NGBE_PSRCTL_MCP MS(8, 0x1) +#define NGBE_PSRCTL_UCP MS(9, 0x1) +#define NGBE_PSRCTL_BCA MS(10, 0x1) +#define NGBE_PSRCTL_L4CSUM MS(12, 0x1) +#define NGBE_PSRCTL_PCSD MS(13, 0x1) +#define NGBE_PSRCTL_LBENA MS(18, 0x1) +#define NGBE_FRMSZ 0x015020 +#define NGBE_FRMSZ_MAX_MASK MS(0, 0xFFFF) +#define NGBE_FRMSZ_MAX(v) LS(v, 0, 0xFFFF) +#define NGBE_VLANCTL 0x015088 +#define NGBE_VLANCTL_TPID_MASK MS(0, 0xFFFF) +#define NGBE_VLANCTL_TPID(v) LS(v, 0, 0xFFFF) +#define NGBE_VLANCTL_CFI MS(28, 0x1) +#define NGBE_VLANCTL_CFIENA MS(29, 0x1) +#define NGBE_VLANCTL_VFE MS(30, 0x1) +#define NGBE_POOLCTL 0x0151B0 +#define NGBE_POOLCTL_DEFDSA MS(29, 0x1) +#define NGBE_POOLCTL_RPLEN MS(30, 0x1) +#define NGBE_POOLCTL_MODE_MASK MS(16, 0x3) +#define NGBE_PSRPOOL_MODE_MAC LS(0, 16, 0x3) +#define NGBE_PSRPOOL_MODE_ETAG LS(1, 16, 0x3) +#define NGBE_POOLCTL_DEFPL(v) LS(v, 7, 0x7) +#define NGBE_POOLCTL_DEFPL_MASK MS(7, 0x7) + +#define NGBE_ETFLT(i) (0x015128 + (i) * 4) /*0-7*/ +#define NGBE_ETFLT_ETID(v) LS(v, 0, 0xFFFF) +#define NGBE_ETFLT_ETID_MASK MS(0, 0xFFFF) +#define NGBE_ETFLT_POOL(v) LS(v, 20, 0x7) +#define NGBE_ETFLT_POOLENA MS(26, 0x1) +#define NGBE_ETFLT_TXAS MS(29, 0x1) +#define NGBE_ETFLT_1588 MS(30, 0x1) +#define NGBE_ETFLT_ENA MS(31, 0x1) +#define NGBE_ETCLS(i) (0x019100 + (i) * 4) /*0-7*/ +#define NGBE_ETCLS_QPID(v) LS(v, 16, 0x7) +#define NGBD_ETCLS_QPID(r) RS(r, 16, 0x7) +#define NGBE_ETCLS_LLI MS(29, 0x1) +#define NGBE_ETCLS_QENA MS(31, 0x1) +#define NGBE_SYNCLS 0x019130 +#define NGBE_SYNCLS_ENA MS(0, 0x1) +#define NGBE_SYNCLS_QPID(v) LS(v, 1, 0x7) +#define NGBD_SYNCLS_QPID(r) RS(r, 1, 0x7) +#define NGBE_SYNCLS_QPID_MASK MS(1, 0x7) +#define NGBE_SYNCLS_HIPRIO MS(31, 0x1) + +/* MAC & VLAN & NVE */ +#define NGBE_PSRVLANIDX 0x016230 /*0-31*/ +#define NGBE_PSRVLAN 0x016220 +#define NGBE_PSRVLAN_VID(v) LS(v, 0, 0xFFF) +#define NGBE_PSRVLAN_EA MS(31, 0x1) +#define NGBE_PSRVLANPLM(i) (0x016224 + (i) * 4) /*0-1*/ + +/** + * Mirror Rules + **/ +#define NGBE_MIRRCTL(i) (0x015B00 + (i) * 4) +#define NGBE_MIRRCTL_POOL MS(0, 0x1) +#define NGBE_MIRRCTL_UPLINK MS(1, 0x1) +#define NGBE_MIRRCTL_DNLINK MS(2, 0x1) +#define NGBE_MIRRCTL_VLAN MS(3, 0x1) +#define NGBE_MIRRCTL_DESTP(v) LS(v, 8, 0x7) +#define NGBE_MIRRVLANL(i) (0x015B10 + (i) * 8) +#define NGBE_MIRRPOOLL(i) (0x015B30 + (i) * 8) + +/** + * Time Stamp + **/ +#define NGBE_TSRXCTL 0x015188 +#define NGBE_TSRXCTL_VLD MS(0, 0x1) +#define NGBE_TSRXCTL_TYPE(v) LS(v, 1, 0x7) +#define NGBE_TSRXCTL_TYPE_V2L2 (0) +#define NGBE_TSRXCTL_TYPE_V1L4 (1) +#define NGBE_TSRXCTL_TYPE_V2L24 (2) +#define NGBE_TSRXCTL_TYPE_V2EVENT (5) +#define NGBE_TSRXCTL_ENA MS(4, 0x1) +#define NGBE_TSRXSTMPL 0x0151E8 +#define NGBE_TSRXSTMPH 0x0151A4 +#define NGBE_TSTXCTL 0x011F00 +#define NGBE_TSTXCTL_VLD MS(0, 0x1) +#define NGBE_TSTXCTL_ENA MS(4, 0x1) +#define NGBE_TSTXSTMPL 0x011F04 +#define NGBE_TSTXSTMPH 0x011F08 +#define NGBE_TSTIMEL 0x011F0C +#define NGBE_TSTIMEH 0x011F10 +#define NGBE_TSTIMEINC 0x011F14 +#define NGBE_TSTIMEINC_IV(v) LS(v, 0, 0x7FFFFFF) + +/** + * Wake on Lan + **/ +#define NGBE_WOLCTL 0x015B80 +#define NGBE_WOLIPCTL 0x015B84 +#define NGBE_WOLIP4(i) (0x015BC0 + (i) * 4) /* 0-3 */ +#define NGBE_WOLIP6(i) (0x015BE0 + (i) * 4) /* 0-3 */ + +#define NGBE_WOLFLEXCTL 0x015CFC +#define NGBE_WOLFLEXI 0x015B8C +#define NGBE_WOLFLEXDAT(i) (0x015C00 + (i) * 16) /* 0-15 */ +#define NGBE_WOLFLEXMSK(i) (0x015C08 + (i) * 16) /* 0-15 */ + +/****************************************************************************** + * Security Registers + ******************************************************************************/ +#define NGBE_SECRXCTL 0x017000 +#define NGBE_SECRXCTL_ODSA MS(0, 0x1) +#define NGBE_SECRXCTL_XDSA MS(1, 0x1) +#define NGBE_SECRXCTL_CRCSTRIP MS(2, 0x1) +#define NGBE_SECRXCTL_SAVEBAD MS(6, 0x1) +#define NGBE_SECRXSTAT 0x017004 +#define NGBE_SECRXSTAT_RDY MS(0, 0x1) +#define NGBE_SECRXSTAT_ECC MS(1, 0x1) + +#define NGBE_SECTXCTL 0x01D000 +#define NGBE_SECTXCTL_ODSA MS(0, 0x1) +#define NGBE_SECTXCTL_XDSA MS(1, 0x1) +#define NGBE_SECTXCTL_STFWD MS(2, 0x1) +#define NGBE_SECTXCTL_MSKIV MS(3, 0x1) +#define NGBE_SECTXSTAT 0x01D004 +#define NGBE_SECTXSTAT_RDY MS(0, 0x1) +#define NGBE_SECTXSTAT_ECC MS(1, 0x1) +#define NGBE_SECTXBUFAF 0x01D008 +#define NGBE_SECTXBUFAE 0x01D00C +#define NGBE_SECTXIFG 0x01D020 +#define NGBE_SECTXIFG_MIN(v) LS(v, 0, 0xF) +#define NGBE_SECTXIFG_MIN_MASK MS(0, 0xF) + +/** + * LinkSec + **/ +#define NGBE_LSECRXCAP 0x017200 +#define NGBE_LSECRXCTL 0x017204 + /* disabled(0),check(1),strict(2),drop(3) */ +#define NGBE_LSECRXCTL_MODE_MASK MS(2, 0x3) +#define NGBE_LSECRXCTL_MODE_STRICT LS(2, 2, 0x3) +#define NGBE_LSECRXCTL_POSTHDR MS(6, 0x1) +#define NGBE_LSECRXCTL_REPLAY MS(7, 0x1) +#define NGBE_LSECRXSCIL 0x017208 +#define NGBE_LSECRXSCIH 0x01720C +#define NGBE_LSECRXSA(i) (0x017210 + (i) * 4) /* 0-1 */ +#define NGBE_LSECRXPN(i) (0x017218 + (i) * 4) /* 0-1 */ +#define NGBE_LSECRXKEY(n, i) (0x017220 + 0x10 * (n) + 4 * (i)) /*0-3*/ +#define NGBE_LSECTXCAP 0x01D200 +#define NGBE_LSECTXCTL 0x01D204 + /* disabled(0), auth(1), auth+encrypt(2) */ +#define NGBE_LSECTXCTL_MODE_MASK MS(0, 0x3) +#define NGBE_LSECTXCTL_MODE_AUTH LS(1, 0, 0x3) +#define NGBE_LSECTXCTL_MODE_AENC LS(2, 0, 0x3) +#define NGBE_LSECTXCTL_PNTRH_MASK MS(8, 0xFFFFFF) +#define NGBE_LSECTXCTL_PNTRH(v) LS(v, 8, 0xFFFFFF) +#define NGBE_LSECTXSCIL 0x01D208 +#define NGBE_LSECTXSCIH 0x01D20C +#define NGBE_LSECTXSA 0x01D210 +#define NGBE_LSECTXPN0 0x01D214 +#define NGBE_LSECTXPN1 0x01D218 +#define NGBE_LSECTXKEY0(i) (0x01D21C + (i) * 4) /* 0-3 */ +#define NGBE_LSECTXKEY1(i) (0x01D22C + (i) * 4) /* 0-3 */ + +#define NGBE_LSECRX_UTPKT 0x017240 +#define NGBE_LSECRX_DECOCT 0x017244 +#define NGBE_LSECRX_VLDOCT 0x017248 +#define NGBE_LSECRX_BTPKT 0x01724C +#define NGBE_LSECRX_NOSCIPKT 0x017250 +#define NGBE_LSECRX_UNSCIPKT 0x017254 +#define NGBE_LSECRX_UNCHKPKT 0x017258 +#define NGBE_LSECRX_DLYPKT 0x01725C +#define NGBE_LSECRX_LATEPKT 0x017260 +#define NGBE_LSECRX_OKPKT(i) (0x017264 + (i) * 4) /* 0-1 */ +#define NGBE_LSECRX_BADPKT(i) (0x01726C + (i) * 4) /* 0-1 */ +#define NGBE_LSECRX_INVPKT(i) (0x017274 + (i) * 4) /* 0-1 */ +#define NGBE_LSECRX_BADSAPKT(i) (0x01727C + (i) * 8) /* 0-3 */ +#define NGBE_LSECRX_INVSAPKT(i) (0x017280 + (i) * 8) /* 0-3 */ +#define NGBE_LSECTX_UTPKT 0x01D23C +#define NGBE_LSECTX_ENCPKT 0x01D240 +#define NGBE_LSECTX_PROTPKT 0x01D244 +#define NGBE_LSECTX_ENCOCT 0x01D248 +#define NGBE_LSECTX_PROTOCT 0x01D24C + +/****************************************************************************** + * MAC Registers + ******************************************************************************/ +#define NGBE_MACRXCFG 0x011004 +#define NGBE_MACRXCFG_ENA MS(0, 0x1) +#define NGBE_MACRXCFG_JUMBO MS(8, 0x1) +#define NGBE_MACRXCFG_LB MS(10, 0x1) +#define NGBE_MACCNTCTL 0x011800 +#define NGBE_MACCNTCTL_RC MS(2, 0x1) + +#define NGBE_MACRXFLT 0x011008 +#define NGBE_MACRXFLT_PROMISC MS(0, 0x1) +#define NGBE_MACRXFLT_CTL_MASK MS(6, 0x3) +#define NGBE_MACRXFLT_CTL_DROP LS(0, 6, 0x3) +#define NGBE_MACRXFLT_CTL_NOPS LS(1, 6, 0x3) +#define NGBE_MACRXFLT_CTL_NOFT LS(2, 6, 0x3) +#define NGBE_MACRXFLT_CTL_PASS LS(3, 6, 0x3) +#define NGBE_MACRXFLT_RXALL MS(31, 0x1) + +/****************************************************************************** + * Statistic Registers + ******************************************************************************/ +/* Ring Counter */ +#define NGBE_QPRXPKT(rp) (0x001014 + 0x40 * (rp)) +#define NGBE_QPRXOCTL(rp) (0x001018 + 0x40 * (rp)) +#define NGBE_QPRXOCTH(rp) (0x00101C + 0x40 * (rp)) +#define NGBE_QPRXMPKT(rp) (0x001020 + 0x40 * (rp)) +#define NGBE_QPRXBPKT(rp) (0x001024 + 0x40 * (rp)) +#define NGBE_QPTXPKT(rp) (0x003014 + 0x40 * (rp)) +#define NGBE_QPTXOCTL(rp) (0x003018 + 0x40 * (rp)) +#define NGBE_QPTXOCTH(rp) (0x00301C + 0x40 * (rp)) +#define NGBE_QPTXMPKT(rp) (0x003020 + 0x40 * (rp)) +#define NGBE_QPTXBPKT(rp) (0x003024 + 0x40 * (rp)) + +/* TDMA Counter */ +#define NGBE_DMATXDROP 0x018300 +#define NGBE_DMATXSECDROP 0x018304 +#define NGBE_DMATXPKT 0x018308 +#define NGBE_DMATXOCTL 0x01830C +#define NGBE_DMATXOCTH 0x018310 +#define NGBE_DMATXMNG 0x018314 + +/* RDMA Counter */ +#define NGBE_DMARXDROP 0x012500 +#define NGBE_DMARXPKT 0x012504 +#define NGBE_DMARXOCTL 0x012508 +#define NGBE_DMARXOCTH 0x01250C +#define NGBE_DMARXMNG 0x012510 + +/* Packet Buffer Counter */ +#define NGBE_PBRXMISS 0x019040 +#define NGBE_PBRXPKT 0x019060 +#define NGBE_PBRXREP 0x019064 +#define NGBE_PBRXDROP 0x019068 +#define NGBE_PBLBSTAT 0x01906C +#define NGBE_PBLBSTAT_FREE(r) RS(r, 0, 0x3FF) +#define NGBE_PBLBSTAT_FULL MS(11, 0x1) +#define NGBE_PBRXWRPTR 0x019180 +#define NGBE_PBRXWRPTR_HEAD(r) RS(r, 0, 0xFFFF) +#define NGBE_PBRXWRPTR_TAIL(r) RS(r, 16, 0xFFFF) +#define NGBE_PBRXRDPTR 0x0191A0 +#define NGBE_PBRXRDPTR_HEAD(r) RS(r, 0, 0xFFFF) +#define NGBE_PBRXRDPTR_TAIL(r) RS(r, 16, 0xFFFF) +#define NGBE_PBRXDATA 0x0191C0 +#define NGBE_PBRXDATA_RDPTR(r) RS(r, 0, 0xFFFF) +#define NGBE_PBRXDATA_WRPTR(r) RS(r, 16, 0xFFFF) +#define NGBE_PBRX_USDSP 0x0191E0 +#define NGBE_RXPBPFCDMACL 0x019210 +#define NGBE_RXPBPFCDMACH 0x019214 +#define NGBE_PBTXLNKXOFF 0x019218 +#define NGBE_PBTXLNKXON 0x01921C + +#define NGBE_PBTXSTAT 0x01C004 +#define NGBE_PBTXSTAT_EMPT(tc, r) ((1 << (tc) & (r)) >> (tc)) + +#define NGBE_PBRXLNKXOFF 0x011988 +#define NGBE_PBRXLNKXON 0x011E0C + +#define NGBE_PBLPBK 0x01CF08 + +/* Ether Flow Counter */ +#define NGBE_LANPKTDROP 0x0151C0 +#define NGBE_MNGPKTDROP 0x0151C4 + +#define NGBE_PSRLANPKTCNT 0x0151B8 +#define NGBE_PSRMNGPKTCNT 0x0151BC + +/* MAC Counter */ +#define NGBE_MACRXERRCRCL 0x011928 +#define NGBE_MACRXERRCRCH 0x01192C +#define NGBE_MACRXERRLENL 0x011978 +#define NGBE_MACRXERRLENH 0x01197C +#define NGBE_MACRX1TO64L 0x001940 +#define NGBE_MACRX1TO64H 0x001944 +#define NGBE_MACRX65TO127L 0x001948 +#define NGBE_MACRX65TO127H 0x00194C +#define NGBE_MACRX128TO255L 0x001950 +#define NGBE_MACRX128TO255H 0x001954 +#define NGBE_MACRX256TO511L 0x001958 +#define NGBE_MACRX256TO511H 0x00195C +#define NGBE_MACRX512TO1023L 0x001960 +#define NGBE_MACRX512TO1023H 0x001964 +#define NGBE_MACRX1024TOMAXL 0x001968 +#define NGBE_MACRX1024TOMAXH 0x00196C +#define NGBE_MACTX1TO64L 0x001834 +#define NGBE_MACTX1TO64H 0x001838 +#define NGBE_MACTX65TO127L 0x00183C +#define NGBE_MACTX65TO127H 0x001840 +#define NGBE_MACTX128TO255L 0x001844 +#define NGBE_MACTX128TO255H 0x001848 +#define NGBE_MACTX256TO511L 0x00184C +#define NGBE_MACTX256TO511H 0x001850 +#define NGBE_MACTX512TO1023L 0x001854 +#define NGBE_MACTX512TO1023H 0x001858 +#define NGBE_MACTX1024TOMAXL 0x00185C +#define NGBE_MACTX1024TOMAXH 0x001860 + +#define NGBE_MACRXUNDERSIZE 0x011938 +#define NGBE_MACRXOVERSIZE 0x01193C +#define NGBE_MACRXJABBER 0x011934 + +#define NGBE_MACRXPKTL 0x011900 +#define NGBE_MACRXPKTH 0x011904 +#define NGBE_MACTXPKTL 0x01181C +#define NGBE_MACTXPKTH 0x011820 +#define NGBE_MACRXGBOCTL 0x011908 +#define NGBE_MACRXGBOCTH 0x01190C +#define NGBE_MACTXGBOCTL 0x011814 +#define NGBE_MACTXGBOCTH 0x011818 + +#define NGBE_MACRXOCTL 0x011918 +#define NGBE_MACRXOCTH 0x01191C +#define NGBE_MACRXMPKTL 0x011920 +#define NGBE_MACRXMPKTH 0x011924 +#define NGBE_MACTXOCTL 0x011824 +#define NGBE_MACTXOCTH 0x011828 +#define NGBE_MACTXMPKTL 0x01182C +#define NGBE_MACTXMPKTH 0x011830 + +/* Management Counter */ +#define NGBE_MNGOUT 0x01CF00 +#define NGBE_MNGIN 0x01CF04 +#define NGBE_MNGDROP 0x01CF0C + +/* MAC SEC Counter */ +#define NGBE_LSECRXUNTAG 0x017240 +#define NGBE_LSECRXDECOCT 0x017244 +#define NGBE_LSECRXVLDOCT 0x017248 +#define NGBE_LSECRXBADTAG 0x01724C +#define NGBE_LSECRXNOSCI 0x017250 +#define NGBE_LSECRXUKSCI 0x017254 +#define NGBE_LSECRXUNCHK 0x017258 +#define NGBE_LSECRXDLY 0x01725C +#define NGBE_LSECRXLATE 0x017260 +#define NGBE_LSECRXGOOD 0x017264 +#define NGBE_LSECRXBAD 0x01726C +#define NGBE_LSECRXUK 0x017274 +#define NGBE_LSECRXBADSA 0x01727C +#define NGBE_LSECRXUKSA 0x017280 +#define NGBE_LSECTXUNTAG 0x01D23C +#define NGBE_LSECTXENC 0x01D240 +#define NGBE_LSECTXPTT 0x01D244 +#define NGBE_LSECTXENCOCT 0x01D248 +#define NGBE_LSECTXPTTOCT 0x01D24C + +/* Management Counter */ +#define NGBE_MNGOS2BMC 0x01E094 +#define NGBE_MNGBMC2OS 0x01E090 + +/****************************************************************************** + * PF(Physical Function) Registers + ******************************************************************************/ +/* Interrupt */ +#define NGBE_ICRMISC 0x000100 +#define NGBE_ICRMISC_MASK MS(8, 0xFFFFFF) +#define NGBE_ICRMISC_RST MS(10, 0x1) /* device reset event */ +#define NGBE_ICRMISC_TS MS(11, 0x1) /* time sync */ +#define NGBE_ICRMISC_STALL MS(12, 0x1) /* trans or recv path is stalled */ +#define NGBE_ICRMISC_LNKSEC MS(13, 0x1) /* Tx LinkSec require key exchange*/ +#define NGBE_ICRMISC_ERRBUF MS(14, 0x1) /* Packet Buffer Overrun */ +#define NGBE_ICRMISC_ERRMAC MS(17, 0x1) /* err reported by MAC */ +#define NGBE_ICRMISC_PHY MS(18, 0x1) /* interrupt reported by eth phy */ +#define NGBE_ICRMISC_ERRIG MS(20, 0x1) /* integrity error */ +#define NGBE_ICRMISC_SPI MS(21, 0x1) /* SPI interface */ +#define NGBE_ICRMISC_VFMBX MS(23, 0x1) /* VF-PF message box */ +#define NGBE_ICRMISC_GPIO MS(26, 0x1) /* GPIO interrupt */ +#define NGBE_ICRMISC_ERRPCI MS(27, 0x1) /* pcie request error */ +#define NGBE_ICRMISC_HEAT MS(28, 0x1) /* overheat detection */ +#define NGBE_ICRMISC_PROBE MS(29, 0x1) /* probe match */ +#define NGBE_ICRMISC_MNGMBX MS(30, 0x1) /* mng mailbox */ +#define NGBE_ICRMISC_TIMER MS(31, 0x1) /* tcp timer */ +#define NGBE_ICRMISC_DEFAULT ( \ + NGBE_ICRMISC_RST | \ + NGBE_ICRMISC_ERRMAC | \ + NGBE_ICRMISC_PHY | \ + NGBE_ICRMISC_ERRIG | \ + NGBE_ICRMISC_GPIO | \ + NGBE_ICRMISC_VFMBX | \ + NGBE_ICRMISC_MNGMBX | \ + NGBE_ICRMISC_STALL | \ + NGBE_ICRMISC_TIMER) +#define NGBE_ICSMISC 0x000104 +#define NGBE_IENMISC 0x000108 +#define NGBE_IVARMISC 0x0004FC +#define NGBE_IVARMISC_VEC(v) LS(v, 0, 0x7) +#define NGBE_IVARMISC_VLD MS(7, 0x1) +#define NGBE_ICR(i) (0x000120 + (i) * 4) /*0*/ +#define NGBE_ICR_MASK MS(0, 0x1FF) +#define NGBE_ICS(i) (0x000130 + (i) * 4) /*0*/ +#define NGBE_ICS_MASK NGBE_ICR_MASK +#define NGBE_IMS(i) (0x000140 + (i) * 4) /*0*/ +#define NGBE_IMS_MASK NGBE_ICR_MASK +#define NGBE_IMC(i) (0x000150 + (i) * 4) /*0*/ +#define NGBE_IMC_MASK NGBE_ICR_MASK +#define NGBE_IVAR(i) (0x000500 + (i) * 4) /*0-3*/ +#define NGBE_IVAR_VEC(v) LS(v, 0, 0x7) +#define NGBE_IVAR_VLD MS(7, 0x1) +#define NGBE_TCPTMR 0x000170 +#define NGBE_ITRSEL 0x000180 + +/* P2V Mailbox */ +#define NGBE_MBMEM(i) (0x005000 + 0x40 * (i)) /*0-7*/ +#define NGBE_MBCTL(i) (0x000600 + 4 * (i)) /*0-7*/ +#define NGBE_MBCTL_STS MS(0, 0x1) /* Initiate message send to VF */ +#define NGBE_MBCTL_ACK MS(1, 0x1) /* Ack message recv'd from VF */ +#define NGBE_MBCTL_VFU MS(2, 0x1) /* VF owns the mailbox buffer */ +#define NGBE_MBCTL_PFU MS(3, 0x1) /* PF owns the mailbox buffer */ +#define NGBE_MBCTL_RVFU MS(4, 0x1) /* Reset VFU - used when VF stuck */ +#define NGBE_MBVFICR 0x000480 +#define NGBE_MBVFICR_INDEX(vf) ((vf) >> 4) +#define NGBE_MBVFICR_VFREQ_MASK (0x0000FFFF) /* bits for VF messages */ +#define NGBE_MBVFICR_VFREQ_VF1 (0x00000001) /* bit for VF 1 message */ +#define NGBE_MBVFICR_VFACK_MASK (0xFFFF0000) /* bits for VF acks */ +#define NGBE_MBVFICR_VFACK_VF1 (0x00010000) /* bit for VF 1 ack */ +#define NGBE_FLRVFP 0x000490 +#define NGBE_FLRVFE 0x0004A0 +#define NGBE_FLRVFEC 0x0004A8 + +/****************************************************************************** + * VF(Virtual Function) Registers + ******************************************************************************/ +#define NGBE_VFPBWRAP 0x000000 +#define NGBE_VFPBWRAP_WRAP MS(0, 0x7) +#define NGBE_VFPBWRAP_EMPT MS(3, 0x1) +#define NGBE_VFSTATUS 0x000004 +#define NGBE_VFSTATUS_UP MS(0, 0x1) +#define NGBE_VFSTATUS_BW_MASK MS(1, 0x7) +#define NGBE_VFSTATUS_BW_1G LS(0x1, 1, 0x7) +#define NGBE_VFSTATUS_BW_100M LS(0x2, 1, 0x7) +#define NGBE_VFSTATUS_BW_10M LS(0x4, 1, 0x7) +#define NGBE_VFSTATUS_BUSY MS(4, 0x1) +#define NGBE_VFSTATUS_LANID MS(8, 0x3) +#define NGBE_VFRST 0x000008 +#define NGBE_VFRST_SET MS(0, 0x1) +#define NGBE_VFMSIXECC 0x00000C +#define NGBE_VFPLCFG 0x000078 +#define NGBE_VFPLCFG_RSV MS(0, 0x1) +#define NGBE_VFPLCFG_PSR(v) LS(v, 1, 0x1F) +#define NGBE_VFPLCFG_PSRL4HDR (0x1) +#define NGBE_VFPLCFG_PSRL3HDR (0x2) +#define NGBE_VFPLCFG_PSRL2HDR (0x4) +#define NGBE_VFPLCFG_PSRTUNHDR (0x8) +#define NGBE_VFPLCFG_PSRTUNMAC (0x10) +#define NGBE_VFICR 0x000100 +#define NGBE_VFICR_MASK LS(3, 0, 0x3) +#define NGBE_VFICR_MBX MS(1, 0x1) +#define NGBE_VFICR_DONE1 MS(0, 0x1) +#define NGBE_VFICS 0x000104 +#define NGBE_VFICS_MASK NGBE_VFICR_MASK +#define NGBE_VFIMS 0x000108 +#define NGBE_VFIMS_MASK NGBE_VFICR_MASK +#define NGBE_VFIMC 0x00010C +#define NGBE_VFIMC_MASK NGBE_VFICR_MASK +#define NGBE_VFGPIE 0x000118 +#define NGBE_VFIVAR(i) (0x000240 + 4 * (i)) /*0-1*/ +#define NGBE_VFIVARMISC 0x000260 +#define NGBE_VFIVAR_ALLOC(v) LS(v, 0, 0x1) +#define NGBE_VFIVAR_VLD MS(7, 0x1) + +#define NGBE_VFMBCTL 0x000600 +#define NGBE_VFMBCTL_REQ MS(0, 0x1) /* Request for PF Ready bit */ +#define NGBE_VFMBCTL_ACK MS(1, 0x1) /* Ack PF message received */ +#define NGBE_VFMBCTL_VFU MS(2, 0x1) /* VF owns the mailbox buffer */ +#define NGBE_VFMBCTL_PFU MS(3, 0x1) /* PF owns the mailbox buffer */ +#define NGBE_VFMBCTL_PFSTS MS(4, 0x1) /* PF wrote a message in the MB */ +#define NGBE_VFMBCTL_PFACK MS(5, 0x1) /* PF ack the previous VF msg */ +#define NGBE_VFMBCTL_RSTI MS(6, 0x1) /* PF has reset indication */ +#define NGBE_VFMBCTL_RSTD MS(7, 0x1) /* PF has indicated reset done */ +#define NGBE_VFMBCTL_R2C_BITS (NGBE_VFMBCTL_RSTD | \ + NGBE_VFMBCTL_PFSTS | \ + NGBE_VFMBCTL_PFACK) +#define NGBE_VFMBX 0x000C00 /*0-15*/ +#define NGBE_VFTPHCTL(i) 0x000D00 + +/****************************************************************************** + * PF&VF TxRx Interface + ******************************************************************************/ +#define RNGLEN(v) ROUND_OVER(v, 13, 7) +#define HDRLEN(v) ROUND_OVER(v, 10, 6) +#define PKTLEN(v) ROUND_OVER(v, 14, 10) +#define INTTHR(v) ROUND_OVER(v, 4, 0) + +#define NGBE_RING_DESC_ALIGN 128 +#define NGBE_RING_DESC_MIN 128 +#define NGBE_RING_DESC_MAX 8192 +#define NGBE_RXD_ALIGN NGBE_RING_DESC_ALIGN +#define NGBE_TXD_ALIGN NGBE_RING_DESC_ALIGN + +/* receive ring */ +#define NGBE_RXBAL(rp) (0x001000 + 0x40 * (rp)) +#define NGBE_RXBAH(rp) (0x001004 + 0x40 * (rp)) +#define NGBE_RXRP(rp) (0x00100C + 0x40 * (rp)) +#define NGBE_RXWP(rp) (0x001008 + 0x40 * (rp)) +#define NGBE_RXCFG(rp) (0x001010 + 0x40 * (rp)) +#define NGBE_RXCFG_ENA MS(0, 0x1) +#define NGBE_RXCFG_RNGLEN(v) LS(RNGLEN(v), 1, 0x3F) +#define NGBE_RXCFG_PKTLEN(v) LS(PKTLEN(v), 8, 0xF) +#define NGBE_RXCFG_PKTLEN_MASK MS(8, 0xF) +#define NGBE_RXCFG_HDRLEN(v) LS(HDRLEN(v), 12, 0xF) +#define NGBE_RXCFG_HDRLEN_MASK MS(12, 0xF) +#define NGBE_RXCFG_WTHRESH(v) LS(v, 16, 0x7) +#define NGBE_RXCFG_ETAG MS(22, 0x1) +#define NGBE_RXCFG_SPLIT MS(26, 0x1) +#define NGBE_RXCFG_CNTAG MS(28, 0x1) +#define NGBE_RXCFG_DROP MS(30, 0x1) +#define NGBE_RXCFG_VLAN MS(31, 0x1) + +/* transmit ring */ +#define NGBE_TXBAL(rp) (0x003000 + 0x40 * (rp)) /*0-7*/ +#define NGBE_TXBAH(rp) (0x003004 + 0x40 * (rp)) +#define NGBE_TXWP(rp) (0x003008 + 0x40 * (rp)) +#define NGBE_TXRP(rp) (0x00300C + 0x40 * (rp)) +#define NGBE_TXCFG(rp) (0x003010 + 0x40 * (rp)) +#define NGBE_TXCFG_ENA MS(0, 0x1) +#define NGBE_TXCFG_BUFLEN_MASK MS(1, 0x3F) +#define NGBE_TXCFG_BUFLEN(v) LS(RNGLEN(v), 1, 0x3F) +#define NGBE_TXCFG_HTHRESH_MASK MS(8, 0xF) +#define NGBE_TXCFG_HTHRESH(v) LS(v, 8, 0xF) +#define NGBE_TXCFG_WTHRESH_MASK MS(16, 0x7F) +#define NGBE_TXCFG_WTHRESH(v) LS(v, 16, 0x7F) +#define NGBE_TXCFG_FLUSH MS(26, 0x1) + +/* interrupt registers */ +#define NGBE_BMEPEND 0x000168 +#define NGBE_BMEPEND_ST MS(0, 0x1) +#define NGBE_ITRI 0x000180 +#define NGBE_ITR(i) (0x000200 + 4 * (i)) +#define NGBE_ITR_IVAL_MASK MS(2, 0x1FFF) /* 1ns/10G, 10ns/REST */ +#define NGBE_ITR_IVAL(v) LS(v, 2, 0x1FFF) /*1ns/10G, 10ns/REST*/ +#define NGBE_ITR_IVAL_1G(us) NGBE_ITR_IVAL((us) / 2) +#define NGBE_ITR_IVAL_10G(us) NGBE_ITR_IVAL((us) / 20) +#define NGBE_ITR_LLIEA MS(15, 0x1) +#define NGBE_ITR_LLICREDIT(v) LS(v, 16, 0x1F) +#define NGBE_ITR_CNT(v) LS(v, 21, 0x3FF) +#define NGBE_ITR_WRDSA MS(31, 0x1) +#define NGBE_GPIE 0x000118 +#define NGBE_GPIE_MSIX MS(0, 0x1) +#define NGBE_GPIE_LLIEA MS(1, 0x1) +#define NGBE_GPIE_LLIVAL(v) LS(v, 3, 0x1F) +#define NGBE_GPIE_LLIVAL_H(v) LS(v, 16, 0x7FF) + +/****************************************************************************** + * Debug Registers + ******************************************************************************/ +/** + * Probe + **/ +#define NGBE_PRBCTL 0x010200 +#define NGBE_PRBSTA 0x010204 +#define NGBE_PRBDAT 0x010220 +#define NGBE_PRBCNT 0x010228 + +#define NGBE_PRBPCI 0x01F010 +#define NGBE_PRBPSR 0x015010 +#define NGBE_PRBRDB 0x019010 +#define NGBE_PRBTDB 0x01C010 +#define NGBE_PRBRSEC 0x017010 +#define NGBE_PRBTSEC 0x01D010 +#define NGBE_PRBMNG 0x01E010 +#define NGBE_PRBRMAC 0x011014 +#define NGBE_PRBTMAC 0x011010 +#define NGBE_PRBREMAC 0x011E04 +#define NGBE_PRBTEMAC 0x011E00 + +/** + * ECC + **/ +#define NGBE_ECCRXPBCTL 0x019014 +#define NGBE_ECCRXPBINJ 0x019018 +#define NGBE_ECCRXPB 0x01901C +#define NGBE_ECCTXPBCTL 0x01C014 +#define NGBE_ECCTXPBINJ 0x01C018 +#define NGBE_ECCTXPB 0x01C01C + +#define NGBE_ECCRXETHCTL 0x015014 +#define NGBE_ECCRXETHINJ 0x015018 +#define NGBE_ECCRXETH 0x01401C + +#define NGBE_ECCRXSECCTL 0x017014 +#define NGBE_ECCRXSECINJ 0x017018 +#define NGBE_ECCRXSEC 0x01701C +#define NGBE_ECCTXSECCTL 0x01D014 +#define NGBE_ECCTXSECINJ 0x01D018 +#define NGBE_ECCTXSEC 0x01D01C + +#define NGBE_P2VMBX_SIZE (16) /* 16*4B */ +#define NGBE_P2MMBX_SIZE (64) /* 64*4B */ + +/**************** Global Registers ****************************/ +#define NGBE_POOLETHCTL(pl) (0x015600 + (pl) * 4) +#define NGBE_POOLETHCTL_LBDIA MS(0, 0x1) +#define NGBE_POOLETHCTL_LLBDIA MS(1, 0x1) +#define NGBE_POOLETHCTL_LLB MS(2, 0x1) +#define NGBE_POOLETHCTL_UCP MS(4, 0x1) +#define NGBE_POOLETHCTL_ETP MS(5, 0x1) +#define NGBE_POOLETHCTL_VLA MS(6, 0x1) +#define NGBE_POOLETHCTL_VLP MS(7, 0x1) +#define NGBE_POOLETHCTL_UTA MS(8, 0x1) +#define NGBE_POOLETHCTL_MCHA MS(9, 0x1) +#define NGBE_POOLETHCTL_UCHA MS(10, 0x1) +#define NGBE_POOLETHCTL_BCA MS(11, 0x1) +#define NGBE_POOLETHCTL_MCP MS(12, 0x1) +#define NGBE_POOLDROPSWBK(i) (0x0151C8 + (i) * 4) /*0-1*/ + +/**************************** Receive DMA registers **************************/ + +#define NGBE_RPUP2TC 0x019008 +#define NGBE_RPUP2TC_UP_SHIFT 3 +#define NGBE_RPUP2TC_UP_MASK 0x7 + +/* mac switcher */ +#define NGBE_ETHADDRL 0x016200 +#define NGBE_ETHADDRL_AD0(v) LS(v, 0, 0xFF) +#define NGBE_ETHADDRL_AD1(v) LS(v, 8, 0xFF) +#define NGBE_ETHADDRL_AD2(v) LS(v, 16, 0xFF) +#define NGBE_ETHADDRL_AD3(v) LS(v, 24, 0xFF) +#define NGBE_ETHADDRL_ETAG(r) RS(r, 0, 0x3FFF) +#define NGBE_ETHADDRH 0x016204 +#define NGBE_ETHADDRH_AD4(v) LS(v, 0, 0xFF) +#define NGBE_ETHADDRH_AD5(v) LS(v, 8, 0xFF) +#define NGBE_ETHADDRH_AD_MASK MS(0, 0xFFFF) +#define NGBE_ETHADDRH_ETAG MS(30, 0x1) +#define NGBE_ETHADDRH_VLD MS(31, 0x1) +#define NGBE_ETHADDRASS 0x016208 +#define NGBE_ETHADDRIDX 0x016210 + +/* Outmost Barrier Filters */ +#define NGBE_MCADDRTBL(i) (0x015200 + (i) * 4) /*0-127*/ +#define NGBE_UCADDRTBL(i) (0x015400 + (i) * 4) /*0-127*/ +#define NGBE_VLANTBL(i) (0x016000 + (i) * 4) /*0-127*/ + +#define NGBE_MNGFLEXSEL 0x1582C +#define NGBE_MNGFLEXDWL(i) (0x15A00 + ((i) * 16)) +#define NGBE_MNGFLEXDWH(i) (0x15A04 + ((i) * 16)) +#define NGBE_MNGFLEXMSK(i) (0x15A08 + ((i) * 16)) + +#define NGBE_LANFLEXSEL 0x15B8C +#define NGBE_LANFLEXDWL(i) (0x15C00 + ((i) * 16)) +#define NGBE_LANFLEXDWH(i) (0x15C04 + ((i) * 16)) +#define NGBE_LANFLEXMSK(i) (0x15C08 + ((i) * 16)) +#define NGBE_LANFLEXCTL 0x15CFC + +/* ipsec */ +#define NGBE_IPSRXIDX 0x017100 +#define NGBE_IPSRXIDX_ENA MS(0, 0x1) +#define NGBE_IPSRXIDX_TB_MASK MS(1, 0x3) +#define NGBE_IPSRXIDX_TB_IP LS(1, 1, 0x3) +#define NGBE_IPSRXIDX_TB_SPI LS(2, 1, 0x3) +#define NGBE_IPSRXIDX_TB_KEY LS(3, 1, 0x3) +#define NGBE_IPSRXIDX_TBIDX(v) LS(v, 3, 0xF) +#define NGBE_IPSRXIDX_READ MS(30, 0x1) +#define NGBE_IPSRXIDX_WRITE MS(31, 0x1) +#define NGBE_IPSRXADDR(i) (0x017104 + (i) * 4) + +#define NGBE_IPSRXSPI 0x017114 +#define NGBE_IPSRXADDRIDX 0x017118 +#define NGBE_IPSRXKEY(i) (0x01711C + (i) * 4) +#define NGBE_IPSRXSALT 0x01712C +#define NGBE_IPSRXMODE 0x017130 +#define NGBE_IPSRXMODE_IPV6 0x00000010 +#define NGBE_IPSRXMODE_DEC 0x00000008 +#define NGBE_IPSRXMODE_ESP 0x00000004 +#define NGBE_IPSRXMODE_AH 0x00000002 +#define NGBE_IPSRXMODE_VLD 0x00000001 +#define NGBE_IPSTXIDX 0x01D100 +#define NGBE_IPSTXIDX_ENA MS(0, 0x1) +#define NGBE_IPSTXIDX_SAIDX(v) LS(v, 3, 0x3FF) +#define NGBE_IPSTXIDX_READ MS(30, 0x1) +#define NGBE_IPSTXIDX_WRITE MS(31, 0x1) +#define NGBE_IPSTXSALT 0x01D104 +#define NGBE_IPSTXKEY(i) (0x01D108 + (i) * 4) + +#define NGBE_MACTXCFG 0x011000 +#define NGBE_MACTXCFG_TE MS(0, 0x1) +#define NGBE_MACTXCFG_SPEED_MASK MS(29, 0x3) +#define NGBE_MACTXCFG_SPEED(v) LS(v, 29, 0x3) +#define NGBE_MACTXCFG_SPEED_10G LS(0, 29, 0x3) +#define NGBE_MACTXCFG_SPEED_1G LS(3, 29, 0x3) + +#define NGBE_ISBADDRL 0x000160 +#define NGBE_ISBADDRH 0x000164 + +#define NGBE_ARBPOOLIDX 0x01820C +#define NGBE_ARBTXRATE 0x018404 +#define NGBE_ARBTXRATE_MIN(v) LS(v, 0, 0x3FFF) +#define NGBE_ARBTXRATE_MAX(v) LS(v, 16, 0x3FFF) + +/* qos */ +#define NGBE_ARBTXCTL 0x018200 +#define NGBE_ARBTXCTL_RRM MS(1, 0x1) +#define NGBE_ARBTXCTL_WSP MS(2, 0x1) +#define NGBE_ARBTXCTL_DIA MS(6, 0x1) +#define NGBE_ARBTXMMW 0x018208 + +/* Management */ +#define NGBE_MNGFWSYNC 0x01E000 +#define NGBE_MNGFWSYNC_REQ MS(0, 0x1) +#define NGBE_MNGSWSYNC 0x01E004 +#define NGBE_MNGSWSYNC_REQ MS(0, 0x1) +#define NGBE_SWSEM 0x01002C +#define NGBE_SWSEM_PF MS(0, 0x1) +#define NGBE_MNGSEM 0x01E008 +#define NGBE_MNGSEM_SW(v) LS(v, 0, 0xFFFF) +#define NGBE_MNGSEM_SWPHY MS(0, 0x1) +#define NGBE_MNGSEM_SWMBX MS(2, 0x1) +#define NGBE_MNGSEM_SWFLASH MS(3, 0x1) +#define NGBE_MNGSEM_FW(v) LS(v, 16, 0xFFFF) +#define NGBE_MNGSEM_FWPHY MS(16, 0x1) +#define NGBE_MNGSEM_FWMBX MS(18, 0x1) +#define NGBE_MNGSEM_FWFLASH MS(19, 0x1) +#define NGBE_MNGMBXCTL 0x01E044 +#define NGBE_MNGMBXCTL_SWRDY MS(0, 0x1) +#define NGBE_MNGMBXCTL_SWACK MS(1, 0x1) +#define NGBE_MNGMBXCTL_FWRDY MS(2, 0x1) +#define NGBE_MNGMBXCTL_FWACK MS(3, 0x1) +#define NGBE_MNGMBX 0x01E100 + +/** + * MDIO(PHY) + **/ +#define NGBE_MDIOSCA 0x011200 +#define NGBE_MDIOSCA_REG(v) LS(v, 0, 0xFFFF) +#define NGBE_MDIOSCA_PORT(v) LS(v, 16, 0x1F) +#define NGBE_MDIOSCA_DEV(v) LS(v, 21, 0x1F) +#define NGBE_MDIOSCD 0x011204 +#define NGBE_MDIOSCD_DAT_R(r) RS(r, 0, 0xFFFF) +#define NGBE_MDIOSCD_DAT(v) LS(v, 0, 0xFFFF) +#define NGBE_MDIOSCD_CMD_PREAD LS(2, 16, 0x3) +#define NGBE_MDIOSCD_CMD_WRITE LS(1, 16, 0x3) +#define NGBE_MDIOSCD_CMD_READ LS(3, 16, 0x3) +#define NGBE_MDIOSCD_SADDR MS(18, 0x1) +#define NGBE_MDIOSCD_CLOCK(v) LS(v, 19, 0x7) +#define NGBE_MDIOSCD_BUSY MS(22, 0x1) + +#define NGBE_MDIOMODE 0x011220 +#define NGBE_MDIOMODE_MASK MS(0, 0xF) +#define NGBE_MDIOMODE_PRT3CL22 MS(3, 0x1) +#define NGBE_MDIOMODE_PRT2CL22 MS(2, 0x1) +#define NGBE_MDIOMODE_PRT1CL22 MS(1, 0x1) +#define NGBE_MDIOMODE_PRT0CL22 MS(0, 0x1) + +#define NVM_OROM_OFFSET 0x17 +#define NVM_OROM_BLK_LOW 0x83 +#define NVM_OROM_BLK_HI 0x84 +#define NVM_OROM_PATCH_MASK 0xFF +#define NVM_OROM_SHIFT 8 +#define NVM_VER_MASK 0x00FF /* version mask */ +#define NVM_VER_SHIFT 8 /* version bit shift */ +#define NVM_OEM_PROD_VER_PTR 0x1B /* OEM Product version block pointer */ +#define NVM_OEM_PROD_VER_CAP_OFF 0x1 /* OEM Product version format offset */ +#define NVM_OEM_PROD_VER_OFF_L 0x2 /* OEM Product version offset low */ +#define NVM_OEM_PROD_VER_OFF_H 0x3 /* OEM Product version offset high */ +#define NVM_OEM_PROD_VER_CAP_MASK 0xF /* OEM Product version cap mask */ +#define NVM_OEM_PROD_VER_MOD_LEN 0x3 /* OEM Product version module length */ +#define NVM_ETK_OFF_LOW 0x2D /* version low order word */ +#define NVM_ETK_OFF_HI 0x2E /* version high order word */ +#define NVM_ETK_SHIFT 16 /* high version word shift */ +#define NVM_VER_INVALID 0xFFFF +#define NVM_ETK_VALID 0x8000 +#define NVM_INVALID_PTR 0xFFFF +#define NVM_VER_SIZE 32 /* version string size */ + +#define NGBE_REG_RSSTBL NGBE_RSSTBL(0) +#define NGBE_REG_RSSKEY NGBE_RSSKEY(0) + +/* + * read non-rc counters + */ +#define NGBE_UPDCNT32(reg, last, cur) \ +do { \ + uint32_t latest = rd32(hw, reg); \ + if (hw->offset_loaded || hw->rx_loaded) \ + last = 0; \ + cur += (latest - last) & UINT_MAX; \ + last = latest; \ +} while (0) + +#define NGBE_UPDCNT36(regl, last, cur) \ +do { \ + uint64_t new_lsb = rd32(hw, regl); \ + uint64_t new_msb = rd32(hw, regl + 4); \ + uint64_t latest = ((new_msb << 32) | new_lsb); \ + if (hw->offset_loaded || hw->rx_loaded) \ + last = 0; \ + cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \ + last = latest; \ +} while (0) + +/** + * register operations + **/ +#define NGBE_REG_READ32(addr) rte_read32(addr) +#define NGBE_REG_READ32_RELAXED(addr) rte_read32_relaxed(addr) +#define NGBE_REG_WRITE32(addr, val) rte_write32(val, addr) +#define NGBE_REG_WRITE32_RELAXED(addr, val) rte_write32_relaxed(val, addr) + +#define NGBE_DEAD_READ_REG 0xdeadbeefU +#define NGBE_FAILED_READ_REG 0xffffffffU +#define NGBE_REG_ADDR(hw, reg) \ + ((volatile u32 *)((char *)(hw)->hw_addr + (reg))) + +static inline u32 +ngbe_get32(volatile u32 *addr) +{ + u32 val = NGBE_REG_READ32(addr); + return rte_le_to_cpu_32(val); +} + +static inline void +ngbe_set32(volatile u32 *addr, u32 val) +{ + val = rte_cpu_to_le_32(val); + NGBE_REG_WRITE32(addr, val); +} + +static inline u32 +ngbe_get32_masked(volatile u32 *addr, u32 mask) +{ + u32 val = ngbe_get32(addr); + val &= mask; + return val; +} + +static inline void +ngbe_set32_masked(volatile u32 *addr, u32 mask, u32 field) +{ + u32 val = ngbe_get32(addr); + val = ((val & ~mask) | (field & mask)); + ngbe_set32(addr, val); +} + +static inline u32 +ngbe_get32_relaxed(volatile u32 *addr) +{ + u32 val = NGBE_REG_READ32_RELAXED(addr); + return rte_le_to_cpu_32(val); +} + +static inline void +ngbe_set32_relaxed(volatile u32 *addr, u32 val) +{ + val = rte_cpu_to_le_32(val); + NGBE_REG_WRITE32_RELAXED(addr, val); +} + +static inline u32 +rd32(struct ngbe_hw *hw, u32 reg) +{ + if (reg == NGBE_REG_DUMMY) + return 0; + return ngbe_get32(NGBE_REG_ADDR(hw, reg)); +} + +static inline void +wr32(struct ngbe_hw *hw, u32 reg, u32 val) +{ + if (reg == NGBE_REG_DUMMY) + return; + ngbe_set32(NGBE_REG_ADDR(hw, reg), val); +} + +static inline u32 +rd32m(struct ngbe_hw *hw, u32 reg, u32 mask) +{ + u32 val = rd32(hw, reg); + val &= mask; + return val; +} + +static inline void +wr32m(struct ngbe_hw *hw, u32 reg, u32 mask, u32 field) +{ + u32 val = rd32(hw, reg); + val = ((val & ~mask) | (field & mask)); + wr32(hw, reg, val); +} + +static inline u64 +rd64(struct ngbe_hw *hw, u32 reg) +{ + u64 lsb = rd32(hw, reg); + u64 msb = rd32(hw, reg + 4); + return (lsb | msb << 32); +} + +static inline void +wr64(struct ngbe_hw *hw, u32 reg, u64 val) +{ + wr32(hw, reg, (u32)val); + wr32(hw, reg + 4, (u32)(val >> 32)); +} + +/* poll register */ +static inline u32 +po32m(struct ngbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual, + u32 loop, u32 slice) +{ + bool usec = true; + u32 value = 0, all = 0; + + if (slice > 1000 * MAX_UDELAY_MS) { + usec = false; + slice = (slice + 500) / 1000; + } + + do { + all |= rd32(hw, reg); + value |= mask & all; + if (value == expect) + break; + + usec ? usec_delay(slice) : msec_delay(slice); + } while (--loop > 0); + + if (actual) + *actual = all; + + return loop; +} + +/* flush all write operations */ +#define ngbe_flush(hw) rd32(hw, 0x00100C) + +#define rd32a(hw, reg, idx) ( \ + rd32((hw), (reg) + ((idx) << 2))) +#define wr32a(hw, reg, idx, val) \ + wr32((hw), (reg) + ((idx) << 2), (val)) + +#define rd32w(hw, reg, mask, slice) do { \ + rd32((hw), reg); \ + po32m((hw), reg, mask, mask, NULL, 5, slice); \ +} while (0) + +#define wr32w(hw, reg, val, mask, slice) do { \ + wr32((hw), reg, val); \ + po32m((hw), reg, mask, mask, NULL, 5, slice); \ +} while (0) + +#define NGBE_XPCS_IDAADDR 0x13000 +#define NGBE_XPCS_IDADATA 0x13004 +#define NGBE_EPHY_IDAADDR 0x13008 +#define NGBE_EPHY_IDADATA 0x1300C +static inline u32 +rd32_epcs(struct ngbe_hw *hw, u32 addr) +{ + u32 data; + wr32(hw, NGBE_XPCS_IDAADDR, addr); + data = rd32(hw, NGBE_XPCS_IDADATA); + return data; +} + +static inline void +wr32_epcs(struct ngbe_hw *hw, u32 addr, u32 data) +{ + wr32(hw, NGBE_XPCS_IDAADDR, addr); + wr32(hw, NGBE_XPCS_IDADATA, data); +} + +static inline u32 +rd32_ephy(struct ngbe_hw *hw, u32 addr) +{ + u32 data; + wr32(hw, NGBE_EPHY_IDAADDR, addr); + data = rd32(hw, NGBE_EPHY_IDADATA); + return data; +} + +static inline void +wr32_ephy(struct ngbe_hw *hw, u32 addr, u32 data) +{ + wr32(hw, NGBE_EPHY_IDAADDR, addr); + wr32(hw, NGBE_EPHY_IDADATA, data); +} + +#endif /* _NGBE_REGS_H_ */ diff --git a/drivers/net/ngbe/base/ngbe_type.h b/drivers/net/ngbe/base/ngbe_type.h index 30d66f109..e3b3e0e69 100644 --- a/drivers/net/ngbe/base/ngbe_type.h +++ b/drivers/net/ngbe/base/ngbe_type.h @@ -25,4 +25,6 @@ struct ngbe_hw { bool is_pf; }; +#include "ngbe_regs.h" + #endif /* _NGBE_TYPE_H_ */ -- 2.21.0.windows.1 ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [dpdk-dev] [PATCH v4 0/6] net: ngbe PMD 2021-04-06 9:30 [dpdk-dev] [PATCH v4 0/6] net: ngbe PMD Jiawen Wu ` (5 preceding siblings ...) 2021-04-06 9:30 ` [dpdk-dev] [PATCH v4 6/6] net/ngbe: define registers Jiawen Wu @ 2021-04-09 14:47 ` Ferruh Yigit 2021-04-29 10:52 ` Jiawen Wu 6 siblings, 1 reply; 14+ messages in thread From: Ferruh Yigit @ 2021-04-09 14:47 UTC (permalink / raw) To: Jiawen Wu, dev On 4/6/2021 10:30 AM, Jiawen Wu wrote: > This patch set provides a skeleton of ngbe PMD, > which adapted to Wangxun WX1860 series NICs. > > v4: > - Fix compile error. > > v3: > - Use rte_ether functions to define marcos. > > v2: > - Correct some clerical errors. > - Use ethdev debug flags instead of driver own. > > Jiawen Wu (6): > net/ngbe: add build and doc infrastructure > net/ngbe: add device IDs > net/ngbe: support probe and remove > net/ngbe: add device init and uninit > net/ngbe: add log type and error type > net/ngbe: define registers > Hi Jiawen, I put some comments on some patches, but as far as I can see the device is not functional yet after this set, I assume rest of the support will be submitted later. But I think the device should have at least bare minimum functionality when it is upstreamed, like proper device initialization and primitive Rx/Tx, also it would be good to have basic control functions. More control and datapath functionality can be added gradually later. What do you think extending this set to have base minimum functionality? Thanks, ferruh ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [dpdk-dev] [PATCH v4 0/6] net: ngbe PMD 2021-04-09 14:47 ` [dpdk-dev] [PATCH v4 0/6] net: ngbe PMD Ferruh Yigit @ 2021-04-29 10:52 ` Jiawen Wu 2021-04-29 11:21 ` Ferruh Yigit 0 siblings, 1 reply; 14+ messages in thread From: Jiawen Wu @ 2021-04-29 10:52 UTC (permalink / raw) To: 'Ferruh Yigit', dev On Friday, April 9, 2021 10:47 PM, Ferruh Yigit wrote: > On 4/6/2021 10:30 AM, Jiawen Wu wrote: > > This patch set provides a skeleton of ngbe PMD, which adapted to > > Wangxun WX1860 series NICs. > > > > v4: > > - Fix compile error. > > > > v3: > > - Use rte_ether functions to define marcos. > > > > v2: > > - Correct some clerical errors. > > - Use ethdev debug flags instead of driver own. > > > > Jiawen Wu (6): > > net/ngbe: add build and doc infrastructure > > net/ngbe: add device IDs > > net/ngbe: support probe and remove > > net/ngbe: add device init and uninit > > net/ngbe: add log type and error type > > net/ngbe: define registers > > > > Hi Jiawen, > > I put some comments on some patches, but as far as I can see the device is not > functional yet after this set, I assume rest of the support will be submitted > later. > But I think the device should have at least bare minimum functionality when it > is upstreamed, like proper device initialization and primitive Rx/Tx, also it would > be good to have basic control functions. > More control and datapath functionality can be added gradually later. > > What do you think extending this set to have base minimum functionality? > > Thanks, > ferruh Hi Ferruh, Unfortunately, this driver may not be merged in 21.05, to follow the roadmap. There is not enough time for me to improve the patches, because I was busy with other works in these weeks. I'll try my best to submit the driver in this release cycle, and hope it will be merged nicely in next release. Thanks. ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [dpdk-dev] [PATCH v4 0/6] net: ngbe PMD 2021-04-29 10:52 ` Jiawen Wu @ 2021-04-29 11:21 ` Ferruh Yigit 0 siblings, 0 replies; 14+ messages in thread From: Ferruh Yigit @ 2021-04-29 11:21 UTC (permalink / raw) To: Jiawen Wu, dev On 4/29/2021 11:52 AM, Jiawen Wu wrote: > On Friday, April 9, 2021 10:47 PM, Ferruh Yigit wrote: >> On 4/6/2021 10:30 AM, Jiawen Wu wrote: >>> This patch set provides a skeleton of ngbe PMD, which adapted to >>> Wangxun WX1860 series NICs. >>> >>> v4: >>> - Fix compile error. >>> >>> v3: >>> - Use rte_ether functions to define marcos. >>> >>> v2: >>> - Correct some clerical errors. >>> - Use ethdev debug flags instead of driver own. >>> >>> Jiawen Wu (6): >>> net/ngbe: add build and doc infrastructure >>> net/ngbe: add device IDs >>> net/ngbe: support probe and remove >>> net/ngbe: add device init and uninit >>> net/ngbe: add log type and error type >>> net/ngbe: define registers >>> >> >> Hi Jiawen, >> >> I put some comments on some patches, but as far as I can see the device is not >> functional yet after this set, I assume rest of the support will be submitted >> later. >> But I think the device should have at least bare minimum functionality when it >> is upstreamed, like proper device initialization and primitive Rx/Tx, also it would >> be good to have basic control functions. >> More control and datapath functionality can be added gradually later. >> >> What do you think extending this set to have base minimum functionality? >> >> Thanks, >> ferruh > > Hi Ferruh, > > Unfortunately, this driver may not be merged in 21.05, to follow the roadmap. > There is not enough time for me to improve the patches, because I was busy with other works in these weeks. > > I'll try my best to submit the driver in this release cycle, and hope it will be merged nicely in next release. > That is OK, thanks for heads up. ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2021-04-29 11:21 UTC | newest] Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-04-06 9:30 [dpdk-dev] [PATCH v4 0/6] net: ngbe PMD Jiawen Wu 2021-04-06 9:30 ` [dpdk-dev] [PATCH v4 1/6] net/ngbe: add build and doc infrastructure Jiawen Wu 2021-04-09 14:37 ` Ferruh Yigit 2021-04-12 6:33 ` Jiawen Wu 2021-04-06 9:30 ` [dpdk-dev] [PATCH v4 2/6] net/ngbe: add device IDs Jiawen Wu 2021-04-09 14:37 ` Ferruh Yigit 2021-04-06 9:30 ` [dpdk-dev] [PATCH v4 3/6] net/ngbe: support probe and remove Jiawen Wu 2021-04-09 14:40 ` Ferruh Yigit 2021-04-06 9:30 ` [dpdk-dev] [PATCH v4 4/6] net/ngbe: add device init and uninit Jiawen Wu 2021-04-06 9:30 ` [dpdk-dev] [PATCH v4 5/6] net/ngbe: add log type and error type Jiawen Wu 2021-04-06 9:30 ` [dpdk-dev] [PATCH v4 6/6] net/ngbe: define registers Jiawen Wu 2021-04-09 14:47 ` [dpdk-dev] [PATCH v4 0/6] net: ngbe PMD Ferruh Yigit 2021-04-29 10:52 ` Jiawen Wu 2021-04-29 11:21 ` Ferruh Yigit
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