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([2a00:23c4:cf2d:a200:6023:b810:2491:c6a9]) by smtp.gmail.com with ESMTPSA id d21sm8131325wrb.51.2020.03.27.04.45.40 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 27 Mar 2020 04:45:40 -0700 (PDT) To: dev@dpdk.org References: <1582778348-113547-15-git-send-email-nicolas.chautru@intel.com> <1585193268-74468-1-git-send-email-nicolas.chautru@intel.com> <1585193268-74468-6-git-send-email-nicolas.chautru@intel.com> From: Dave Burley Message-ID: Date: Fri, 27 Mar 2020 11:45:40 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <1585193268-74468-6-git-send-email-nicolas.chautru@intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US Subject: Re: [dpdk-dev] [PATCH v5 05/10] test-bbdev: rename FPGA LTE macros to be more explicit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Acked-by: Dave Burley On 26/03/2020 03:27, Nicolas Chautru wrote: > From: Nic Chautru > > Self-contained and cosmetic renaming of macro > so that to be more explicit for future extension. > > Signed-off-by: Nic Chautru > --- > app/test-bbdev/test_bbdev_perf.c | 51 +++++++++++++++------------------------- > 1 file changed, 19 insertions(+), 32 deletions(-) > > diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c > index e998d0b..b17fc95 100644 > --- a/app/test-bbdev/test_bbdev_perf.c > +++ b/app/test-bbdev/test_bbdev_perf.c > @@ -18,10 +18,6 @@ > #include > #include > > -#ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC > -#include > -#endif > - > #include "main.h" > #include "test_bbdev_vector.h" > > @@ -31,15 +27,16 @@ > #define TEST_REPETITIONS 1000 > > #ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC > -#define FPGA_PF_DRIVER_NAME ("intel_fpga_lte_fec_pf") > -#define FPGA_VF_DRIVER_NAME ("intel_fpga_lte_fec_vf") > -#define VF_UL_QUEUE_VALUE 4 > -#define VF_DL_QUEUE_VALUE 4 > -#define UL_BANDWIDTH 3 > -#define DL_BANDWIDTH 3 > -#define UL_LOAD_BALANCE 128 > -#define DL_LOAD_BALANCE 128 > -#define FLR_TIMEOUT 610 > +#include > +#define FPGA_LTE_PF_DRIVER_NAME ("intel_fpga_lte_fec_pf") > +#define FPGA_LTE_VF_DRIVER_NAME ("intel_fpga_lte_fec_vf") > +#define VF_UL_4G_QUEUE_VALUE 4 > +#define VF_DL_4G_QUEUE_VALUE 4 > +#define UL_4G_BANDWIDTH 3 > +#define DL_4G_BANDWIDTH 3 > +#define UL_4G_LOAD_BALANCE 128 > +#define DL_4G_LOAD_BALANCE 128 > +#define FLR_4G_TIMEOUT 610 > #endif > > #define OPS_CACHE_SIZE 256U > @@ -521,11 +518,11 @@ typedef int (test_case_function)(struct active_device *ad, > */ > #ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC > if ((get_init_device() == true) && > - (!strcmp(info->drv.driver_name, FPGA_PF_DRIVER_NAME))) { > + (!strcmp(info->drv.driver_name, FPGA_LTE_PF_DRIVER_NAME))) { > struct fpga_lte_fec_conf conf; > unsigned int i; > > - printf("Configure FPGA FEC Driver %s with default values\n", > + printf("Configure FPGA LTE FEC Driver %s with default values\n", > info->drv.driver_name); > > /* clear default configuration before initialization */ > @@ -539,22 +536,22 @@ typedef int (test_case_function)(struct active_device *ad, > > for (i = 0; i < FPGA_LTE_FEC_NUM_VFS; ++i) { > /* Number of UL queues per VF (fpga supports 8 VFs) */ > - conf.vf_ul_queues_number[i] = VF_UL_QUEUE_VALUE; > + conf.vf_ul_queues_number[i] = VF_UL_4G_QUEUE_VALUE; > /* Number of DL queues per VF (fpga supports 8 VFs) */ > - conf.vf_dl_queues_number[i] = VF_DL_QUEUE_VALUE; > + conf.vf_dl_queues_number[i] = VF_DL_4G_QUEUE_VALUE; > } > > /* UL bandwidth. Needed for schedule algorithm */ > - conf.ul_bandwidth = UL_BANDWIDTH; > + conf.ul_bandwidth = UL_4G_BANDWIDTH; > /* DL bandwidth */ > - conf.dl_bandwidth = DL_BANDWIDTH; > + conf.dl_bandwidth = DL_4G_BANDWIDTH; > > /* UL & DL load Balance Factor to 64 */ > - conf.ul_load_balance = UL_LOAD_BALANCE; > - conf.dl_load_balance = DL_LOAD_BALANCE; > + conf.ul_load_balance = UL_4G_LOAD_BALANCE; > + conf.dl_load_balance = DL_4G_LOAD_BALANCE; > > /**< FLR timeout value */ > - conf.flr_time_out = FLR_TIMEOUT; > + conf.flr_time_out = FLR_4G_TIMEOUT; > > /* setup FPGA PF with configuration information */ > ret = fpga_lte_fec_configure(info->dev_name, &conf); > @@ -2856,11 +2853,6 @@ typedef int (test_case_function)(struct active_device *ad, > > start_time = rte_rdtsc_precise(); > > - /* > - * printf("Latency Debug %d\n", > - * ops_enq[0]->ldpc_enc.cb_params.z_c); REMOVEME > - */ > - > enq = rte_bbdev_enqueue_ldpc_enc_ops(dev_id, queue_id, > &ops_enq[enq], burst_sz); > TEST_ASSERT(enq == burst_sz, > @@ -2886,11 +2878,6 @@ typedef int (test_case_function)(struct active_device *ad, > TEST_ASSERT_SUCCESS(ret, "Validation failed!"); > } > > - /* > - * printf("Ready to free - deq %d num_to_process %d\n", FIXME > - * deq, num_to_process); > - * printf("cache %d\n", ops_enq[0]->mempool->cache_size); > - */ > rte_bbdev_enc_op_free_bulk(ops_enq, deq); > dequeued += deq; > }