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From: "Mattias Rönnblom" <mattias.ronnblom@ericsson.com>
To: "dev@dpdk.org" <dev@dpdk.org>,
	Bruce Richardson <bruce.richardson@intel.com>
Cc: Maria Lingemark <maria.lingemark@ericsson.com>
Subject: Bogus TSC frequency on Skylake
Date: Tue, 24 May 2022 14:11:15 +0000	[thread overview]
Message-ID: <a630c4cb-e806-0898-f3a0-61c85cabedb0@ericsson.com> (raw)

Hi.

I just wanted to call to attention the bug
https://bugs.dpdk.org/show_bug.cgi?id=959

A drift of 0.1% on (certain?) Skylake Xeons is pretty significant, and 
will force some applications to use the slower clock_gettime() syscall 
instead of rte_get_timer_cycles() to retrieve wall time.

I can look into if we can provide a patch, but I'm guessing certain 
Intel employees are in a better position to find out which CPUs you can 
trust the reported TSC frequency, and which you cannot.

Also, the rounding to an even 10 MHz (for the fallback TSC calculation) 
should probably go away, since the TSC rate doesn't seem to come in such 
steps any more.

Regards,
	Mattias

                 reply	other threads:[~2022-05-24 14:11 UTC|newest]

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