From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 37403A0C4A; Tue, 13 Jul 2021 03:07:12 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AD0144069E; Tue, 13 Jul 2021 03:07:11 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 3B1754069D for ; Tue, 13 Jul 2021 03:07:10 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10043"; a="273910437" X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="273910437" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 18:07:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="561937044" Received: from fmsmsx604.amr.corp.intel.com ([10.18.126.84]) by orsmga004.jf.intel.com with ESMTP; 12 Jul 2021 18:07:08 -0700 Received: from shsmsx602.ccr.corp.intel.com (10.109.6.142) by fmsmsx604.amr.corp.intel.com (10.18.126.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.10; Mon, 12 Jul 2021 18:07:07 -0700 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by SHSMSX602.ccr.corp.intel.com (10.109.6.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.10; Tue, 13 Jul 2021 09:07:05 +0800 Received: from shsmsx601.ccr.corp.intel.com ([10.109.6.141]) by SHSMSX601.ccr.corp.intel.com ([10.109.6.141]) with mapi id 15.01.2242.010; Tue, 13 Jul 2021 09:07:05 +0800 From: "Zhang, Qi Z" To: "Su, Simei" CC: "dev@dpdk.org" , "Cao, Yahui" Thread-Topic: [PATCH] net/ice: fix SPI for ESP and NATT not work issue Thread-Index: AQHXdwMAgT0UV3x4l0enmba/VLzjmKtAFyOw Date: Tue, 13 Jul 2021 01:07:05 +0000 Message-ID: References: <20210712093914.441114-1-simei.su@intel.com> In-Reply-To: <20210712093914.441114-1-simei.su@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] net/ice: fix SPI for ESP and NATT not work issue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Su, Simei > Sent: Monday, July 12, 2021 5:39 PM > To: Zhang, Qi Z > Cc: dev@dpdk.org; Cao, Yahui ; Su, Simei > > Subject: [PATCH] net/ice: fix SPI for ESP and NATT not work issue What is "ESP and NATT"=20 Do you mean=20 fix FDIR when SPI as inputset for an ESP over UDP Flow ? >=20 > This patch fixes this issue by adding the correspongding input set for ES= P and s/ correspongding/corresponding > NATT when parsing input set. Also, it adds input set bit for NAT_T_ESP to > distinguish ESP over IP and ESP over UDP. >=20 > Fixes: 70feafc1a3f2 ("net/ice: support ESP/NATT flow director to match ou= ter > IP") >=20 > Signed-off-by: Simei Su > --- > drivers/net/ice/ice_fdir_filter.c | 14 ++++++++++---- > drivers/net/ice/ice_generic_flow.h | 3 +++ > 2 files changed, 13 insertions(+), 4 deletions(-) >=20 > diff --git a/drivers/net/ice/ice_fdir_filter.c b/drivers/net/ice/ice_fdir= _filter.c > index 4f1aa39..82adb1f 100644 > --- a/drivers/net/ice/ice_fdir_filter.c > +++ b/drivers/net/ice/ice_fdir_filter.c > @@ -100,11 +100,11 @@ >=20 > #define ICE_FDIR_INSET_IPV4_NATT_ESP (\ > ICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | \ > - ICE_INSET_ESP_SPI) > + ICE_INSET_NAT_T_ESP_SPI) >=20 > #define ICE_FDIR_INSET_IPV6_NATT_ESP (\ > ICE_INSET_IPV6_SRC | ICE_INSET_IPV6_DST | \ > - ICE_INSET_ESP_SPI) > + ICE_INSET_NAT_T_ESP_SPI) >=20 > static struct ice_pattern_match_item ice_fdir_pattern_list[] =3D { > {pattern_ethertype, ICE_FDIR_INSET_ETH, > ICE_INSET_NONE, ICE_INSET_NONE}, > @@ -951,6 +951,8 @@ ice_fdir_input_set_parse(uint64_t inset, enum > ice_flow_field *field) > {ICE_INSET_GTPU_TEID, ICE_FLOW_FIELD_IDX_GTPU_IP_TEID}, > {ICE_INSET_GTPU_QFI, ICE_FLOW_FIELD_IDX_GTPU_EH_QFI}, > {ICE_INSET_VXLAN_VNI, ICE_FLOW_FIELD_IDX_VXLAN_VNI}, > + {ICE_INSET_ESP_SPI, ICE_FLOW_FIELD_IDX_ESP_SPI}, > + {ICE_INSET_NAT_T_ESP_SPI, > ICE_FLOW_FIELD_IDX_NAT_T_ESP_SPI}, > }; >=20 > for (i =3D 0, j =3D 0; i < RTE_DIM(ice_inset_map); i++) { @@ -2128,8 +2= 130,12 > @@ ice_fdir_parse_pattern(__rte_unused struct ice_adapter *ad, > if (!(esp_spec && esp_mask)) > break; >=20 > - if (esp_mask->hdr.spi =3D=3D UINT32_MAX) > - *input_set |=3D ICE_INSET_ESP_SPI; > + if (esp_mask->hdr.spi =3D=3D UINT32_MAX) { > + if (l4 =3D=3D RTE_FLOW_ITEM_TYPE_UDP) > + *input_set |=3D ICE_INSET_NAT_T_ESP_SPI; > + else > + *input_set |=3D ICE_INSET_ESP_SPI; > + } >=20 > if (l3 =3D=3D RTE_FLOW_ITEM_TYPE_IPV4) > filter->input.ip.v4.sec_parm_idx =3D > diff --git a/drivers/net/ice/ice_generic_flow.h > b/drivers/net/ice/ice_generic_flow.h > index 0bd38d8..8845a3e 100644 > --- a/drivers/net/ice/ice_generic_flow.h > +++ b/drivers/net/ice/ice_generic_flow.h > @@ -26,6 +26,7 @@ > #define ICE_PROT_AH BIT_ULL(15) > #define ICE_PROT_L2TPV3OIP BIT_ULL(16) > #define ICE_PROT_PFCP BIT_ULL(17) > +#define ICE_PROT_NAT_T_ESP BIT_ULL(18) >=20 > /* field */ >=20 > @@ -117,6 +118,8 @@ > (ICE_PROT_PFCP | ICE_PFCP_S_FIELD) > #define ICE_INSET_PFCP_SEID \ > (ICE_PROT_PFCP | ICE_PFCP_S_FIELD | ICE_PFCP_SEID) > +#define ICE_INSET_NAT_T_ESP_SPI \ > + (ICE_PROT_NAT_T_ESP | ICE_ESP_SPI) >=20 > /* empty pattern */ > extern enum rte_flow_item_type pattern_empty[]; > -- > 2.9.5