From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1C273A054A; Fri, 19 Feb 2021 09:52:51 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8DFC140395; Fri, 19 Feb 2021 09:52:50 +0100 (CET) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id C4C7740042 for ; Fri, 19 Feb 2021 09:52:48 +0100 (CET) IronPort-SDR: eOWeMBoGuSEfKLL2pRoGPQ78YAVA54W784jtCl8QbAH+sIkBR/pbULwW980U60Jls1hwV67MuZ XqFQ6QWTKUBg== X-IronPort-AV: E=McAfee;i="6000,8403,9899"; a="182992448" X-IronPort-AV: E=Sophos;i="5.81,189,1610438400"; d="scan'208";a="182992448" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2021 00:52:38 -0800 IronPort-SDR: gnRvtC+gabBux5NfHg3rtKwmR4nFlahiYJWtfKoDisnVT1Fk8dY65YSQ5jed7RQLczFe0+mQcb wE3GmY+miiQQ== X-IronPort-AV: E=Sophos;i="5.81,189,1610438400"; d="scan'208";a="386791554" Received: from fyigit-mobl1.ger.corp.intel.com (HELO [10.213.251.55]) ([10.213.251.55]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2021 00:52:36 -0800 From: Ferruh Yigit To: =?UTF-8?B?6LCi5Y2O5LyfKOatpOaXtuatpOWIu++8iQ==?= , maxime.coquelin@redhat.com Cc: dev@dpdk.org, david.marchand@redhat.com, anatoly.burakov@intel.com, xuemingl@nvidia.com, grive@u256.net, chenbo.xia@intel.com References: <1611890309-99135-1-git-send-email-huawei.xhw@alibaba-inc.com> <1611890309-99135-3-git-send-email-huawei.xhw@alibaba-inc.com> X-User: ferruhy Message-ID: Date: Fri, 19 Feb 2021 08:52:35 +0000 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH v6 2/2] bus/pci: support MMIO in PCI ioport accessors X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 2/9/2021 2:51 PM, Ferruh Yigit wrote: > On 1/29/2021 3:18 AM, 谢华伟(此时此刻） wrote: >> From: "huawei.xhw" >> >> With IO BAR, we get PIO(programmed IO) address. >> With MMIO BAR, we get mapped virtual address. >> We distinguish PIO(Programmed IO) and MMIO(memory mapped IO) by their address >> like how kernel does. >> ioread/write8/16/32 is provided to access PIO/MMIO. >> By the way, for virtio on arch other than x86, BAR flag indicates PIO but is >> mapped. >> >> Signed-off-by: huawei xie >> Reviewed-by: Maxime Coquelin > > <...> > >> +static inline void iowrite8(uint8_t val, void *addr) >> +{ >> +    (uint64_t)(uintptr_t)addr >= PIO_MAX ? >> +        *(volatile uint8_t *)addr = val : >> +        outb(val, (unsigned long)addr); > > Is the 'outb_p' to 'outb' conversion intentional? And if so why? > > Same of the all 'outb_p', 'outw_p', 'outl_p'. > Reminder of above question. Let's try to close this patch before release pressure hit again. And as far as I understand already a new version is required for build errors on non x86 architectures. > <...> > >>               size = 1; >> -#if defined(RTE_ARCH_X86) >> -            outb_p(*s, reg); >> -#else >> -            *(volatile uint8_t *)reg = *s; >> -#endif >> +            iowrite8(*s, (void *)reg); >>           } >>       } >>   } >> >