From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1AFB745501; Wed, 26 Jun 2024 14:05:13 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 82EB84348C; Wed, 26 Jun 2024 13:56:59 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by mails.dpdk.org (Postfix) with ESMTP id 6CB7842E95 for ; Wed, 26 Jun 2024 13:45:25 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719402325; x=1750938325; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TcXu/1rJ8ieQeP0kb2CkKIZi9GJMBdIyfr7dI2poNQw=; b=K7SkaCVcbphIrQAALphgFkInDl18kD8hbSQCvYyfs9zCPRDeoNVYayUm Wmbj5no6as3/8wLpeBW36Rn5glOzCu6VfwWxJRL/YT1jcz6mBz9ef8xOY ZM0De+3kvdWfVrvYyJMIDHtWqwAlOH3OHKUafF11FGDVxtzthghbXJjQz 0UOEJxE960jhDYRmsOcTWd91o6+Hzfx1ANcFdmFtO2jC7wqECLUY5EDMA 9eybIaHYuFAl6GLrhAhquaSpd3D513HNHZ0fjj3QHzyHfs0Y82clSnwGZ CxL0D7fSmPdkqaAye8JVdtEbJP/38kJ9pyg7TaIZp3ZCWnt4W4mWlf1Jz g==; X-CSE-ConnectionGUID: BzSEk/ooSc+Jz825zq1nDA== X-CSE-MsgGUID: CUb5+ZgGSgmgzmijGqx+Fg== X-IronPort-AV: E=McAfee;i="6700,10204,11114"; a="38979559" X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="38979559" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jun 2024 04:45:25 -0700 X-CSE-ConnectionGUID: PgTwZ7B8SrKMRLZKbWmjMQ== X-CSE-MsgGUID: tsNCATuEQ3+Rr6b8IEIPxQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="43874354" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa010.jf.intel.com with ESMTP; 26 Jun 2024 04:45:24 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Fabio Pricoco , ian.stokes@intel.com, bruce.richardson@intel.com Subject: [PATCH v4 085/103] net/ice/base: use a variable to store reset count Date: Wed, 26 Jun 2024 12:42:13 +0100 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Fabio Pricoco Depending on platform and whether silicon validation tools are used, the timeout value may be set to a different value. This patch uses a variable to store the reset count value as opposed to using the macro directly. Signed-off-by: Fabio Pricoco Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_common.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index ca8087dec1..c14f66d55b 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -1236,7 +1236,7 @@ void ice_deinit_hw(struct ice_hw *hw) */ int ice_check_reset(struct ice_hw *hw) { - u32 cnt, reg = 0, grst_timeout, uld_mask; + u32 cnt, reg = 0, grst_timeout, uld_mask, reset_wait_cnt; /* Poll for Device Active state in case a recent CORER, GLOBR, * or EMPR has occurred. The grst delay value is in 100ms units. @@ -1267,8 +1267,10 @@ int ice_check_reset(struct ice_hw *hw) uld_mask = ICE_RESET_DONE_MASK; + reset_wait_cnt = ICE_PF_RESET_WAIT_COUNT; + /* Device is Active; check Global Reset processes are done */ - for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { + for (cnt = 0; cnt < reset_wait_cnt; cnt++) { reg = rd32(hw, GLNVM_ULD) & uld_mask; if (reg == uld_mask) { ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); @@ -1277,7 +1279,7 @@ int ice_check_reset(struct ice_hw *hw) ice_msec_delay(10, true); } - if (cnt == ICE_PF_RESET_WAIT_COUNT) { + if (cnt == reset_wait_cnt) { ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", reg); return ICE_ERR_RESET_FAILED; @@ -1295,7 +1297,7 @@ int ice_check_reset(struct ice_hw *hw) */ static int ice_pf_reset(struct ice_hw *hw) { - u32 cnt, reg; + u32 cnt, reg, reset_wait_cnt, cfg_lock_timeout; /* If at function entry a global reset was already in progress, i.e. * state is not 'device active' or any of the reset done bits are not @@ -1320,8 +1322,10 @@ static int ice_pf_reset(struct ice_hw *hw) * timeout plus the PFR timeout which will account for a possible reset * that is occurring during a download package operation. */ - for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + - ICE_PF_RESET_WAIT_COUNT; cnt++) { + reset_wait_cnt = ICE_PF_RESET_WAIT_COUNT; + cfg_lock_timeout = ICE_GLOBAL_CFG_LOCK_TIMEOUT; + + for (cnt = 0; cnt < cfg_lock_timeout + reset_wait_cnt; cnt++) { reg = rd32(hw, PFGEN_CTRL); if (!(reg & PFGEN_CTRL_PFSWR_M)) break; @@ -1329,7 +1333,7 @@ static int ice_pf_reset(struct ice_hw *hw) ice_msec_delay(1, true); } - if (cnt == ICE_PF_RESET_WAIT_COUNT) { + if (cnt == cfg_lock_timeout + reset_wait_cnt) { ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); return ICE_ERR_RESET_FAILED; } -- 2.43.0