From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 63BA2A0547; Sun, 26 Sep 2021 13:16:44 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CC1884003D; Sun, 26 Sep 2021 13:16:43 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id A02064003C for ; Sun, 26 Sep 2021 13:16:41 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10118"; a="204488256" X-IronPort-AV: E=Sophos;i="5.85,323,1624345200"; d="scan'208";a="204488256" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Sep 2021 04:16:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,323,1624345200"; d="scan'208";a="536785516" Received: from fmsmsx602.amr.corp.intel.com ([10.18.126.82]) by fmsmga004.fm.intel.com with ESMTP; 26 Sep 2021 04:16:40 -0700 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Sun, 26 Sep 2021 04:16:39 -0700 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by SHSMSX601.ccr.corp.intel.com (10.109.6.141) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Sun, 26 Sep 2021 19:16:37 +0800 Received: from shsmsx601.ccr.corp.intel.com ([10.109.6.141]) by SHSMSX601.ccr.corp.intel.com ([10.109.6.141]) with mapi id 15.01.2242.012; Sun, 26 Sep 2021 19:16:37 +0800 From: "Zhang, Qi Z" To: "Su, Simei" CC: "dev@dpdk.org" , "Wang, Haiyue" Thread-Topic: [PATCH v4] net/ice: support IEEE 1588 PTP for E810 Thread-Index: AQHXr4+SvlBGBYwpcEWWKQXTR5rJA6u2LniQ Date: Sun, 26 Sep 2021 11:16:37 +0000 Message-ID: References: <20210909013028.443974-1-simei.su@intel.com> <20210922084633.166409-1-simei.su@intel.com> In-Reply-To: <20210922084633.166409-1-simei.su@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.6.200.16 dlp-product: dlpe-windows x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v4] net/ice: support IEEE 1588 PTP for E810 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Su, Simei > Sent: Wednesday, September 22, 2021 4:47 PM > To: Zhang, Qi Z > Cc: dev@dpdk.org; Wang, Haiyue ; Su, Simei > > Subject: [PATCH v4] net/ice: support IEEE 1588 PTP for E810 No need to mention E810, net/ice already imply its E810. >=20 > Add ice support for new ethdev APIs to enable/disable and read/write/adju= st > IEEE1588 PTP timstamps. Currently, only scalar path supports 1588 PTP, ve= ctor > path doesn't. timestamps >=20 > The example command for running ptpclient is as below: > ./build/examples/dpdk-ptpclient -c 1 -n 3 -- -T 0 -p 0x1 >=20 > Signed-off-by: Simei Su > --- > v4: > * Rework code to consider ice_dev_start and ice_timesync_enable order. >=20 > v3: > * Rework code to support scalar path only. > * Update the doc/guides/nics/features/ice.ini to add "Timesync" feature. > * Add release notes. >=20 > v2: > * Change patchset to one patch based on share code update. > * Change per device offload to per queue offload. >=20 > doc/guides/nics/features/ice.ini | 1 + > doc/guides/rel_notes/release_21_11.rst | 2 +- > drivers/net/ice/ice_ethdev.c | 193 > +++++++++++++++++++++++++++++++++ > drivers/net/ice/ice_ethdev.h | 6 + > drivers/net/ice/ice_rxtx.c | 46 +++++++- > 5 files changed, 245 insertions(+), 3 deletions(-) >=20 > diff --git a/doc/guides/nics/features/ice.ini b/doc/guides/nics/features/= ice.ini > index e066787..a7978d2 100644 > --- a/doc/guides/nics/features/ice.ini > +++ b/doc/guides/nics/features/ice.ini > @@ -43,6 +43,7 @@ Linux =3D Y > Windows =3D Y > x86-32 =3D Y > x86-64 =3D Y > +Timesync =3D Y >=20 > [rte_flow items] > ah =3D Y > diff --git a/doc/guides/rel_notes/release_21_11.rst > b/doc/guides/rel_notes/release_21_11.rst > index 1b9dac6..2005262 100644 > --- a/doc/guides/rel_notes/release_21_11.rst > +++ b/doc/guides/rel_notes/release_21_11.rst > @@ -71,7 +71,7 @@ New Features >=20 > Added 1PPS out support by a devargs. > * Added Rx timstamp support by dynamic mbuf on Flex Descriptor. > - > + * Added timesync API support under scalar path for E810. >=20 > Removed Items > ------------- > diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c = index > 06adf43..26491c3 100644 > --- a/drivers/net/ice/ice_ethdev.c > +++ b/drivers/net/ice/ice_ethdev.c > @@ -18,6 +18,7 @@ > #include "base/ice_flow.h" > #include "base/ice_dcb.h" > #include "base/ice_common.h" > +#include "base/ice_ptp_hw.h" >=20 > #include "rte_pmd_ice.h" > #include "ice_ethdev.h" > @@ -31,6 +32,8 @@ > #define ICE_HW_DEBUG_MASK_ARG "hw_debug_mask" > #define ICE_ONE_PPS_OUT_ARG "pps_out" >=20 > +#define ICE_CYCLECOUNTER_MASK 0xffffffffffffffffULL > + > uint64_t ice_timestamp_dynflag; > int ice_timestamp_dynfield_offset =3D -1; >=20 > @@ -149,6 +152,18 @@ static int ice_dev_udp_tunnel_port_add(struct > rte_eth_dev *dev, > struct rte_eth_udp_tunnel *udp_tunnel); static int > ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, > struct rte_eth_udp_tunnel *udp_tunnel); > +static int ice_timesync_enable(struct rte_eth_dev *dev); static int > +ice_timesync_read_rx_timestamp(struct rte_eth_dev *dev, > + struct timespec *timestamp, > + uint32_t flags); > +static int ice_timesync_read_tx_timestamp(struct rte_eth_dev *dev, > + struct timespec *timestamp); > +static int ice_timesync_adjust_time(struct rte_eth_dev *dev, int64_t > +delta); static int ice_timesync_read_time(struct rte_eth_dev *dev, > + struct timespec *timestamp); > +static int ice_timesync_write_time(struct rte_eth_dev *dev, > + const struct timespec *timestamp); static int > +ice_timesync_disable(struct rte_eth_dev *dev); >=20 > static const struct rte_pci_id pci_id_ice_map[] =3D { > { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, > ICE_DEV_ID_E823L_BACKPLANE) }, @@ -232,6 +247,13 @@ static const struct > eth_dev_ops ice_eth_dev_ops =3D { > .udp_tunnel_port_del =3D ice_dev_udp_tunnel_port_del, > .tx_done_cleanup =3D ice_tx_done_cleanup, > .get_monitor_addr =3D ice_get_monitor_addr, > + .timesync_enable =3D ice_timesync_enable, > + .timesync_read_rx_timestamp =3D ice_timesync_read_rx_timestamp, > + .timesync_read_tx_timestamp =3D ice_timesync_read_tx_timestamp, > + .timesync_adjust_time =3D ice_timesync_adjust_time, > + .timesync_read_time =3D ice_timesync_read_time, > + .timesync_write_time =3D ice_timesync_write_time, > + .timesync_disable =3D ice_timesync_disable, > }; >=20 > /* store statistics names and its offset in stats structure */ @@ -5488,= 6 > +5510,177 @@ ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, } >=20 > static int > +ice_timesync_enable(struct rte_eth_dev *dev) { > + struct ice_hw *hw =3D ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); > + struct ice_adapter *ad =3D > + ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); > + int ret; > + > + if (!dev->data->dev_started) > + ad->ptp_ena =3D 1; Please move ptp_ena =3D1 to end of the function. And when this flag be reset ? > + else { > + if (!(dev->data->dev_conf.rxmode.offloads & > + DEV_RX_OFFLOAD_TIMESTAMP)) { > + PMD_DRV_LOG(ERR, "Rx timestamp offload not configured"); > + return -1; > + } else > + ad->ptp_ena =3D 1; > + } > + > + if (hw->func_caps.ts_func_info.src_tmr_owned) { > + ret =3D ice_ptp_init_phc(hw); > + if (ret) { > + PMD_DRV_LOG(ERR, "Failed to initialize PHC"); > + return -1; > + } > + > + ret =3D ice_ptp_write_incval(hw, ICE_PTP_NOMINAL_INCVAL_E810); > + if (ret) { > + PMD_DRV_LOG(ERR, > + "Failed to write PHC increment time value"); > + return -1; > + } > + } > + > + /* Initialize cycle counters for system time/RX/TX timestamp */ > + memset(&ad->systime_tc, 0, sizeof(struct rte_timecounter)); > + memset(&ad->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); > + memset(&ad->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); > + > + ad->systime_tc.cc_mask =3D ICE_CYCLECOUNTER_MASK; > + ad->systime_tc.cc_shift =3D 0; > + ad->systime_tc.nsec_mask =3D 0; > + > + ad->rx_tstamp_tc.cc_mask =3D ICE_CYCLECOUNTER_MASK; > + ad->rx_tstamp_tc.cc_shift =3D 0; > + ad->rx_tstamp_tc.nsec_mask =3D 0; > + > + ad->tx_tstamp_tc.cc_mask =3D ICE_CYCLECOUNTER_MASK; > + ad->tx_tstamp_tc.cc_shift =3D 0; > + ad->tx_tstamp_tc.nsec_mask =3D 0; > + > + return 0; > +} > + > +static int > +ice_timesync_read_rx_timestamp(struct rte_eth_dev *dev, > + struct timespec *timestamp, uint32_t flags) { > + struct ice_hw *hw =3D ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); > + struct ice_adapter *ad =3D > + ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); > + struct ice_rx_queue *rxq; > + uint32_t ts_high; > + uint64_t time, ts_ns, ns; > + > + rxq =3D dev->data->rx_queues[flags]; > + > + time =3D ice_read_time(hw); > + > + ts_high =3D rxq->time_high; > + ts_ns =3D ice_tstamp_convert_32b_64b(time, ts_high); > + ns =3D rte_timecounter_update(&ad->rx_tstamp_tc, ts_ns); > + *timestamp =3D rte_ns_to_timespec(ns); > + > + return 0; > +} > + > +static int > +ice_timesync_read_tx_timestamp(struct rte_eth_dev *dev, > + struct timespec *timestamp) > +{ > + struct ice_hw *hw =3D ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); > + struct ice_adapter *ad =3D > + ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); > + uint8_t lport; > + uint64_t time, ts_ns, ns, tstamp; > + const uint64_t mask =3D 0xFFFFFFFF; > + int ret; > + > + lport =3D hw->port_info->lport; > + > + ret =3D ice_read_phy_tstamp(hw, lport, 0, &tstamp); > + if (ret) { > + PMD_DRV_LOG(ERR, "Failed to read phy timestamp"); > + return -1; > + } > + > + time =3D ice_read_time(hw); > + > + ts_ns =3D ice_tstamp_convert_32b_64b(time, (tstamp >> 8) & mask); > + ns =3D rte_timecounter_update(&ad->tx_tstamp_tc, ts_ns); > + *timestamp =3D rte_ns_to_timespec(ns); > + > + return 0; > +} > + > +static int > +ice_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) { > + struct ice_adapter *ad =3D > + ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); > + > + ad->systime_tc.nsec +=3D delta; > + ad->rx_tstamp_tc.nsec +=3D delta; > + ad->tx_tstamp_tc.nsec +=3D delta; > + > + return 0; > +} > + > +static int > +ice_timesync_write_time(struct rte_eth_dev *dev, const struct timespec > +*ts) { > + struct ice_adapter *ad =3D > + ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); > + uint64_t ns; > + > + ns =3D rte_timespec_to_ns(ts); > + > + ad->systime_tc.nsec =3D ns; > + ad->rx_tstamp_tc.nsec =3D ns; > + ad->tx_tstamp_tc.nsec =3D ns; > + > + return 0; > +} > + > +static int > +ice_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) { > + struct ice_hw *hw =3D ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); > + struct ice_adapter *ad =3D > + ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); > + uint64_t time, ns; > + > + time =3D ice_read_time(hw); > + ns =3D rte_timecounter_update(&ad->systime_tc, time); > + *ts =3D rte_ns_to_timespec(ns); > + > + return 0; > +} > + > +static int > +ice_timesync_disable(struct rte_eth_dev *dev) { > + struct ice_hw *hw =3D ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); > + uint64_t val; > + uint8_t lport; > + > + lport =3D hw->port_info->lport; > + > + ice_clear_phy_tstamp(hw, lport, 0); > + > + val =3D ICE_READ_REG(hw, GLTSYN_ENA(0)); > + val &=3D ~GLTSYN_ENA_TSYN_ENA_M; > + ICE_WRITE_REG(hw, GLTSYN_ENA(0), val); > + > + ICE_WRITE_REG(hw, GLTSYN_INCVAL_L(0), 0); > + ICE_WRITE_REG(hw, GLTSYN_INCVAL_H(0), 0); > + > + return 0; > +} > + > +static int > ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, > struct rte_pci_device *pci_dev) > { > diff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h = index > ea9d892..448e186 100644 > --- a/drivers/net/ice/ice_ethdev.h > +++ b/drivers/net/ice/ice_ethdev.h > @@ -6,6 +6,7 @@ > #define _ICE_ETHDEV_H_ >=20 > #include > +#include >=20 > #include >=20 > @@ -501,6 +502,11 @@ struct ice_adapter { > struct ice_devargs devargs; > enum ice_pkg_type active_pkg_type; /* loaded ddp package type */ > uint16_t fdir_ref_cnt; > + /* For PTP */ > + struct rte_timecounter systime_tc; > + struct rte_timecounter rx_tstamp_tc; > + struct rte_timecounter tx_tstamp_tc; > + bool ptp_ena; > #ifdef RTE_ARCH_X86 > bool rx_use_avx2; > bool rx_use_avx512; > diff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c inde= x > 717d3f0..5b2aa32 100644 > --- a/drivers/net/ice/ice_rxtx.c > +++ b/drivers/net/ice/ice_rxtx.c > @@ -270,6 +270,7 @@ ice_program_hw_rx_queue(struct ice_rx_queue *rxq) > struct rte_eth_rxmode *rxmode =3D &dev_data->dev_conf.rxmode; > uint32_t rxdid =3D ICE_RXDID_COMMS_OVS; > uint32_t regval; > + struct ice_adapter *ad =3D rxq->vsi->adapter; >=20 > /* Set buffer size as the head split is disabled. */ > buf_size =3D (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) - @@ -366,7 > +367,10 @@ ice_program_hw_rx_queue(struct ice_rx_queue *rxq) > regval |=3D (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) & > QRXFLXP_CNTXT_RXDID_PRIO_M; >=20 > - if (rxq->offloads & DEV_RX_OFFLOAD_TIMESTAMP) > + if (!ad->ptp_ena) { > + if (rxq->offloads & DEV_RX_OFFLOAD_TIMESTAMP) > + regval |=3D QRXFLXP_CNTXT_TS_M; > + } else > regval |=3D QRXFLXP_CNTXT_TS_M; Please simplify above logic.