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Fri, 25 Jul 2025 13:57:04 +0000 Date: Fri, 25 Jul 2025 14:56:58 +0100 From: Bruce Richardson To: Ciara Loftus CC: Subject: Re: [RFC PATCH 06/14] net/ice: use the new common vector capability function Message-ID: References: <20250725124919.3564890-1-ciara.loftus@intel.com> <20250725124919.3564890-7-ciara.loftus@intel.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20250725124919.3564890-7-ciara.loftus@intel.com> X-ClientProxiedBy: DU2P251CA0006.EURP251.PROD.OUTLOOK.COM (2603:10a6:10:230::7) To CY8PR11MB7290.namprd11.prod.outlook.com (2603:10b6:930:9a::6) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY8PR11MB7290:EE_|CO1PR11MB4962:EE_ X-MS-Office365-Filtering-Correlation-Id: 7a903a58-65a8-4712-a4e6-08ddcb83229e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|366016|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?KYCrhO+kkiCNrkS4FYg/bZkeankaqGUzZeEpdEv141s+qPN6w97IFWIixdyK?= =?us-ascii?Q?rLvob7J1OeBtgoRfZ/u1zIYz1ageb9MhG4S2si27GXexpHERDV5vpoC0jmvN?= =?us-ascii?Q?fT35JWeOwXTUAAGSp0Auvg9Jb5GG9kZ70mpIvpsN4CDXpQXQizXB1CRgcMS4?= =?us-ascii?Q?DDZEtFFmMwFfMQe35rMisGUQgWWdhrXz4LCraQQHxb8oALxTjAMb+ecpqGtR?= =?us-ascii?Q?Exz2xGFzd5BHqVhP7Xw0v1pf0KT7v0N6ZVP6ydek/clMQtk0OEdlbKg6ClKC?= =?us-ascii?Q?ZT1TuT7Db6g+gkQviIBMfLgMqhVs/EqR8dab42J72Yb/MUK18JhnU08/SMlp?= =?us-ascii?Q?rLYzfdFRtd8w7y07LIAlV528AGaqefpd/nO6uqGhhgEHZK3+Qc5h60yneD/0?= =?us-ascii?Q?Ux8gNLroVN8TtO5nz0bei+uJIQZpKeOmRHt3NpMrZ+KlZhxGGOKS2QEm/QFi?= =?us-ascii?Q?FXCejhRflovZCSI5v2x43OBA9jgMmPBI8APXkXL0FMoiMhM+Ln0yTmHI+26U?= =?us-ascii?Q?jsSfg8rpXl1SItaXV5VMWc5UNjzOygEG/dR7ZtVxuS0p/wovyqQzaFrpL6Rd?= =?us-ascii?Q?awovD0FO/CBzeIoIPjLd2jTXS7bLBxpYinjZ1zKhKsHmUPx9c0fcmTLOMqzB?= =?us-ascii?Q?FIVf9DGjVpOVzQfWoglHAc9Mtwclrmwej1rmtMI4BF/ONuvFy8Noadr+ECba?= =?us-ascii?Q?x2+v6ZZA4qYPhjpyzIsLAVh7TbpQE2u4IrM5mJRjwe94dai1LiL4f14W88H6?= =?us-ascii?Q?nZBt7Ebn8qQWEDyydyg8BNYzcvWHrd4EZxskMF9FR/EERgbXXG3wTuc016Kq?= =?us-ascii?Q?wCHS1i40DhbJo4yt83M92SfnOo3DYuBEbgkrMyNHX9Zde9uCjMyxIB821CPB?= =?us-ascii?Q?djGphTbc81EHgFoBcXubbnqsM8oigZwMlK07jAHQJSoWSE6KEa0GXoaWKzZX?= =?us-ascii?Q?vo8jSswycIvzmyq2/1VG6XW0Mf3lXjR7soa7YQvRXY/xPGcEUFiQeTb886XV?= =?us-ascii?Q?3UmCRfi07BVgXBFjkGyxQsXiQsVoa7wvWuuc4j0LRFErCHIXGMcX6G4P8hfF?= =?us-ascii?Q?hen+S/i5cVVjhFfUJnaEBBFNVwmeugIoiFScdJEKR91PohJo5uSgZgaWP/Qs?= =?us-ascii?Q?HgmzLsaxiYAoYwsl9Uf9Ek7t4Guv4RAHw105U+sAz3ghoHJc6sAtciTVbHhz?= =?us-ascii?Q?XcWqZr3bcBItzJXcZRKrCMBwcoUzJZcte9jzejUvc4NFeLVzxxmnxuPWlvH7?= =?us-ascii?Q?+QQ8McqQb9yrP/iLgDfH5OcPO1EnyrBRJlkb00EOWrVILIBuV4So0LHVYw4H?= =?us-ascii?Q?HXIwzO9Tor/vVzHuPEVb5b5dS6AZv9vvToWa1CNlerJU6oz4sU/FDeCz+//O?= =?us-ascii?Q?JwO/YBN9IPEOR84LVSuM42Ft5rzPbDlql1s/d4Vq/U1gK4Rb8A=3D=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255; 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> struct ice_parser *psr; > - /* used only on X86, zero on other Archs */ > - bool tx_use_avx2; > - bool tx_use_avx512; > + enum rte_vect_max_simd tx_simd_width; > bool rx_vec_offload_support; > }; > > diff --git a/drivers/net/intel/ice/ice_rxtx.c b/drivers/net/intel/ice/ice_rxtx.c > index 85832d95a3..79217249b9 100644 > --- a/drivers/net/intel/ice/ice_rxtx.c > +++ b/drivers/net/intel/ice/ice_rxtx.c > @@ -3703,7 +3703,7 @@ ice_set_rx_function(struct rte_eth_dev *dev) > struct ci_rx_queue *rxq; > int i; > int rx_check_ret = -1; > - bool rx_use_avx512 = false, rx_use_avx2 = false; > + enum rte_vect_max_simd rx_simd_width = RTE_VECT_SIMD_DISABLED; > > rx_check_ret = ice_rx_vec_dev_check(dev); > if (ad->ptp_ena) > @@ -3720,35 +3720,22 @@ ice_set_rx_function(struct rte_eth_dev *dev) > break; > } > } > + rx_simd_width = ice_get_max_simd_bitwidth(); > Since this whole block is in #ifdef X86_64, do we need a generic ice function here? Is it worth just just calling the x86 function directly? > - if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 && > - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 && > - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1) > -#ifdef CC_AVX512_SUPPORT > - rx_use_avx512 = true; > -#else > - PMD_DRV_LOG(NOTICE, > - "AVX512 is not supported in build env"); > -#endif > - if (!rx_use_avx512 && > - (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || > - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && > - rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256) > - rx_use_avx2 = true; > } else { > ad->rx_vec_allowed = false; > } > > if (ad->rx_vec_allowed) { > if (dev->data->scattered_rx) { > - if (rx_use_avx512) { > + if (rx_simd_width == RTE_VECT_SIMD_512) { > #ifdef CC_AVX512_SUPPORT > if (ad->rx_vec_offload_support) > ad->rx_func_type = ICE_RX_AVX512_SCATTERED_OFFLOAD; > else > ad->rx_func_type = ICE_RX_AVX512_SCATTERED; > #endif > - } else if (rx_use_avx2) { > + } else if (rx_simd_width == RTE_VECT_SIMD_256) { > if (ad->rx_vec_offload_support) > ad->rx_func_type = ICE_RX_AVX2_SCATTERED_OFFLOAD; > else > @@ -3757,14 +3744,14 @@ ice_set_rx_function(struct rte_eth_dev *dev) > ad->rx_func_type = ICE_RX_SSE_SCATTERED; > } > } else { > - if (rx_use_avx512) { > + if (rx_simd_width == RTE_VECT_SIMD_512) { > #ifdef CC_AVX512_SUPPORT > if (ad->rx_vec_offload_support) > ad->rx_func_type = ICE_RX_AVX512_OFFLOAD; > else > ad->rx_func_type = ICE_RX_AVX512; > #endif > - } else if (rx_use_avx2) { > + } else if (rx_simd_width == RTE_VECT_SIMD_256) { > if (ad->rx_vec_offload_support) > ad->rx_func_type = ICE_RX_AVX2_OFFLOAD; > else > @@ -4032,29 +4019,14 @@ ice_set_tx_function(struct rte_eth_dev *dev) > int tx_check_ret = -1; > > if (rte_eal_process_type() == RTE_PROC_PRIMARY) { > - ad->tx_use_avx2 = false; > - ad->tx_use_avx512 = false; > + ad->tx_simd_width = RTE_VECT_SIMD_DISABLED; > tx_check_ret = ice_tx_vec_dev_check(dev); > + ad->tx_simd_width = ice_get_max_simd_bitwidth(); > if (tx_check_ret >= 0 && > rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { > ad->tx_vec_allowed = true; > > - if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 && > - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 && > - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1) > -#ifdef CC_AVX512_SUPPORT > - ad->tx_use_avx512 = true; > -#else > - PMD_DRV_LOG(NOTICE, > - "AVX512 is not supported in build env"); > -#endif > - if (!ad->tx_use_avx512 && > - (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || > - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && > - rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256) > - ad->tx_use_avx2 = true; > - > - if (!ad->tx_use_avx2 && !ad->tx_use_avx512 && > + if (ad->tx_simd_width < RTE_VECT_SIMD_256 && > tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) > ad->tx_vec_allowed = false; > > @@ -4074,7 +4046,7 @@ ice_set_tx_function(struct rte_eth_dev *dev) > > if (ad->tx_vec_allowed) { > dev->tx_pkt_prepare = NULL; > - if (ad->tx_use_avx512) { > + if (ad->tx_simd_width == RTE_VECT_SIMD_512) { > #ifdef CC_AVX512_SUPPORT > if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) { > PMD_DRV_LOG(NOTICE, > @@ -4100,9 +4072,9 @@ ice_set_tx_function(struct rte_eth_dev *dev) > dev->tx_pkt_prepare = ice_prep_pkts; > } else { > PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).", > - ad->tx_use_avx2 ? "avx2 " : "", > + ad->tx_simd_width == RTE_VECT_SIMD_256 ? "avx2 " : "", > dev->data->port_id); > - dev->tx_pkt_burst = ad->tx_use_avx2 ? > + dev->tx_pkt_burst = ad->tx_simd_width == RTE_VECT_SIMD_256 ? > ice_xmit_pkts_vec_avx2 : > ice_xmit_pkts_vec; > } > diff --git a/drivers/net/intel/ice/ice_rxtx.h b/drivers/net/intel/ice/ice_rxtx.h > index 0301d05888..8c3d6c413a 100644 > --- a/drivers/net/intel/ice/ice_rxtx.h > +++ b/drivers/net/intel/ice/ice_rxtx.h > @@ -261,6 +261,7 @@ uint16_t ice_xmit_pkts_vec_avx512_offload(void *tx_queue, > int ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc); > int ice_tx_done_cleanup(void *txq, uint32_t free_cnt); > int ice_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc); > +enum rte_vect_max_simd ice_get_max_simd_bitwidth(void); > > #define FDIR_PARSING_ENABLE_PER_QUEUE(ad, on) do { \ > int i; \ > diff --git a/drivers/net/intel/ice/ice_rxtx_vec_sse.c b/drivers/net/intel/ice/ice_rxtx_vec_sse.c > index d818b3b728..1545bc3b6e 100644 > --- a/drivers/net/intel/ice/ice_rxtx_vec_sse.c > +++ b/drivers/net/intel/ice/ice_rxtx_vec_sse.c > @@ -735,3 +735,9 @@ ice_tx_vec_dev_check(struct rte_eth_dev *dev) > { > return ice_tx_vec_dev_check_default(dev); > } > + > +enum rte_vect_max_simd > +ice_get_max_simd_bitwidth(void) > +{ > + return ci_get_x86_max_simd_bitwidth(); > +} If we do wrap the x86 bitwidth function in an ice-specific one, we probably need to provide one for other architectures. However, as I comment above, I don't think we need to wrap this - though perhaps I'm missing something or its needed in later patches... > -- > 2.34.1 >