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Mon, 11 Aug 2025 17:03:59 +0000 Date: Mon, 11 Aug 2025 18:03:54 +0100 From: Bruce Richardson To: Ciara Loftus CC: Subject: Re: [PATCH v2 13/15] net/ice: use the common Rx path selection infrastructure Message-ID: References: <20250725124919.3564890-1-ciara.loftus@intel.com> <20250807123949.4063416-1-ciara.loftus@intel.com> <20250807123949.4063416-14-ciara.loftus@intel.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20250807123949.4063416-14-ciara.loftus@intel.com> X-ClientProxiedBy: DU6P191CA0066.EURP191.PROD.OUTLOOK.COM (2603:10a6:10:53e::6) To DS0PR11MB7309.namprd11.prod.outlook.com (2603:10b6:8:13e::17) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR11MB7309:EE_|DS0PR11MB7849:EE_ X-MS-Office365-Filtering-Correlation-Id: ae444fbd-ef97-4808-310d-08ddd8f910b5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?1hfgwRbZQc4C18hlMn9lzKCNMTQc4xstCwXQMYn1kVT5A99Zx/k3REL8w6Qe?= =?us-ascii?Q?YT1nGeWxC0bdGhuomnuMbY7Hdy5NueRvLRecEZaeh6clSGtpAZ8TMT4Ulszq?= =?us-ascii?Q?WAR2KCHa0SQ4A/gtCt473spNdHtRZCIdZXXgJCEBDgR4+lvGm5KSXuqnWsnu?= =?us-ascii?Q?KC+ZT8b7d3Ke5jK8MdSKwxTZqbRsipbYkigJl6RHmC9UBFzdQyHm7pTFUuo8?= =?us-ascii?Q?rlaJnzUImQSxqA0T6FwP5i4miaxusRcasx8B6LKjnHyo6WxJ6XE92/bm1SQH?= =?us-ascii?Q?NVJnJcKrJAEsMwQtvfHwk7HxeRwxNXHxoVivnIqOa7fQ0quoT88hXBFks2+L?= =?us-ascii?Q?D3y0PimNcryZpTrrx60Tp8syIjMoZaufEtfM6FYHE+yYW0CGefIwan3HxWAY?= =?us-ascii?Q?jusFHYJZq2eE1tCRyUCgFyWD3sX4XgocDfo7MoegoEjT/+INRhbD1BwiqpXc?= =?us-ascii?Q?vChYjx3E4SASBb28OykPfEDlDYUwEymw9K+sg4c5qG2Td1KSdJ8pvmRe+C8Q?= =?us-ascii?Q?j9qRfQY6qXgIMmcp7uQKRAbq85ZCuJbjKCQSRbOX3bXKWMzFTYD8uP1Z59ge?= =?us-ascii?Q?mNpWzz2VJIv8ugR/hHI/ma3xIdkBVgD/N5cVfIGNaekhbeNJjpSkGAH1+opT?= =?us-ascii?Q?npXzNOes4qJt44gh2aP1SVAVXTfmxdgRSnOeSYN5rVRuyWekq6y3euvGa84/?= =?us-ascii?Q?8+r4u1QqV+C8Yn9jboWoRFlvV7i4nPncUS1V3GhOeMxEDAbdVyqajMpn39v/?= =?us-ascii?Q?Yjbgs94lYqQbT20qJESCnK2XqIadhjbf2eVxfSyDlcIitD7ae2QKUgmfNRs9?= =?us-ascii?Q?h+qXZqWpZdwPxy41hG+zhaVmqXchML8UYY0loUDA3B4hRxy7thlqJnV/5bDE?= =?us-ascii?Q?8rar+ov0PGIlS0hyKEcu3FlMfDHkxfjbUb8NsEcFXc0cGF4R7BiUyds5W6t8?= =?us-ascii?Q?6TrzcrNRf3xEqoYWxxc1PlcA13/z2KEk/enwnfPVrSQoh71HODRDaUxZV5Xg?= =?us-ascii?Q?yMustAyHdRTvVWQ9pOnYFouhc8FhWfjwJRFHA9p98g2P/eWUMPUnvbHBLdFV?= =?us-ascii?Q?hHJrU5JBaeay4PfsSs8KAa6u2exeWu7LjtoHBB9JHkmmBUwcX0bNkUANf8Ae?= =?us-ascii?Q?1jLWZ41tDyHo+kVTZnRfXpSNeEXn5ZHyrgCJNCdCIEP3lwV3tKh5FfT3GSu2?= =?us-ascii?Q?7ggOvFok6X83Chrle/sIv2QewgHMZTcc8xFCghJ323yW+MjPeEjnh/+gp3H/?= =?us-ascii?Q?Gk9liNfrqybSH/sMWI0dY/QZh/XL5lQ8zZoa95e9mTUxvZ/NeKu3XqWGVfkU?= =?us-ascii?Q?5fHWaUeMgY0ws7KDnQU59jHTSc+K8UcgFm7vM3rTB7nLHIEgzlo1IHE52V3E?= =?us-ascii?Q?lYyoYxbHUVG+1IT7au9hGA5YZ514jgNSHAJkenItBrPaWE0/yOwEq7KK//UB?= =?us-ascii?Q?6lDEQJCKFsQ=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255; 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> struct ice_pf pf; > bool rx_bulk_alloc_allowed; > - bool rx_vec_allowed; > bool tx_vec_allowed; > bool tx_simple_allowed; > enum ice_rx_func_type rx_func_type; > diff --git a/drivers/net/intel/ice/ice_rxtx.c b/drivers/net/intel/ice/ice_rxtx.c > index 8c197eefa9..b54edd7a6a 100644 > --- a/drivers/net/intel/ice/ice_rxtx.c > +++ b/drivers/net/intel/ice/ice_rxtx.c > @@ -3662,28 +3662,46 @@ ice_xmit_pkts_simple(void *tx_queue, > return nb_tx; > } > > -static const struct { > - eth_rx_burst_t pkt_burst; > - const char *info; > -} ice_rx_burst_infos[] = { > - [ICE_RX_DEFAULT] = { ice_recv_pkts, "Scalar" }, > - [ICE_RX_SCATTERED] = { ice_recv_scattered_pkts, "Scalar Scattered" }, > - [ICE_RX_BULK_ALLOC] = { ice_recv_pkts_bulk_alloc, "Scalar Bulk Alloc" }, > +static const struct ci_rx_path_info ice_rx_path_infos[] = { > + [ICE_RX_DEFAULT] = { > + ice_recv_pkts, "Scalar", > + {ICE_RX_SCALAR_OFFLOADS, RTE_VECT_SIMD_DISABLED, 0, 0, 0, 0}}, > + [ICE_RX_SCATTERED] = {ice_recv_scattered_pkts, "Scalar Scattered", > + {ICE_RX_SCALAR_OFFLOADS, RTE_VECT_SIMD_DISABLED, CI_RX_PATH_SCATTERED, 0, 0, 0}}, > + [ICE_RX_BULK_ALLOC] = {ice_recv_pkts_bulk_alloc, "Scalar Bulk Alloc", > + {ICE_RX_SCALAR_OFFLOADS, RTE_VECT_SIMD_DISABLED, 0, 0, CI_RX_PATH_BULK_ALLOC, 0}}, > #ifdef RTE_ARCH_X86 > - [ICE_RX_SSE] = { ice_recv_pkts_vec, "Vector SSE" }, > - [ICE_RX_SSE_SCATTERED] = { ice_recv_scattered_pkts_vec, "Vector SSE Scattered" }, > - [ICE_RX_AVX2] = { ice_recv_pkts_vec_avx2, "Vector AVX2" }, > - [ICE_RX_AVX2_SCATTERED] = { ice_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" }, > - [ICE_RX_AVX2_OFFLOAD] = { ice_recv_pkts_vec_avx2_offload, "Offload Vector AVX2" }, > + [ICE_RX_SSE] = {ice_recv_pkts_vec, "Vector SSE", > + {ICE_RX_VECTOR_OFFLOAD_OFFLOADS, RTE_VECT_SIMD_128, > + 0, 0, CI_RX_PATH_BULK_ALLOC, 0}}, > + [ICE_RX_SSE_SCATTERED] = {ice_recv_scattered_pkts_vec, "Vector SSE Scattered", > + {ICE_RX_VECTOR_OFFLOAD_OFFLOADS, RTE_VECT_SIMD_128, > + CI_RX_PATH_SCATTERED, 0, CI_RX_PATH_BULK_ALLOC, 0}}, > + [ICE_RX_AVX2] = {ice_recv_pkts_vec_avx2, "Vector AVX2", > + {ICE_RX_VECTOR_OFFLOADS, RTE_VECT_SIMD_256, 0, 0, CI_RX_PATH_BULK_ALLOC, 0}}, > + [ICE_RX_AVX2_SCATTERED] = {ice_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered", > + {ICE_RX_VECTOR_OFFLOADS, RTE_VECT_SIMD_256, > + CI_RX_PATH_SCATTERED, 0, CI_RX_PATH_BULK_ALLOC, 0}}, > + [ICE_RX_AVX2_OFFLOAD] = {ice_recv_pkts_vec_avx2_offload, "Offload Vector AVX2", > + {ICE_RX_VECTOR_OFFLOAD_OFFLOADS, RTE_VECT_SIMD_256, > + 0, 0, CI_RX_PATH_BULK_ALLOC, 0}}, > [ICE_RX_AVX2_SCATTERED_OFFLOAD] = { > - ice_recv_scattered_pkts_vec_avx2_offload, "Offload Vector AVX2 Scattered" }, > + ice_recv_scattered_pkts_vec_avx2_offload, "Offload Vector AVX2 Scattered", > + {ICE_RX_VECTOR_OFFLOAD_OFFLOADS, RTE_VECT_SIMD_256, > + CI_RX_PATH_SCATTERED, 0, CI_RX_PATH_BULK_ALLOC, 0}}, > #ifdef CC_AVX512_SUPPORT > - [ICE_RX_AVX512] = { ice_recv_pkts_vec_avx512, "Vector AVX512" }, > - [ICE_RX_AVX512_SCATTERED] = { > - ice_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" }, > - [ICE_RX_AVX512_OFFLOAD] = { ice_recv_pkts_vec_avx512_offload, "Offload Vector AVX512" }, > + [ICE_RX_AVX512] = {ice_recv_pkts_vec_avx512, "Vector AVX512", > + {ICE_RX_VECTOR_OFFLOADS, RTE_VECT_SIMD_512, 0, 0, CI_RX_PATH_BULK_ALLOC, 0}}, > + [ICE_RX_AVX512_SCATTERED] = {ice_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered", > + {ICE_RX_VECTOR_OFFLOADS, RTE_VECT_SIMD_512, > + CI_RX_PATH_SCATTERED, 0, CI_RX_PATH_BULK_ALLOC, 0}}, > + [ICE_RX_AVX512_OFFLOAD] = {ice_recv_pkts_vec_avx512_offload, "Offload Vector AVX512", > + {ICE_RX_VECTOR_OFFLOAD_OFFLOADS, RTE_VECT_SIMD_512, > + 0, 0, CI_RX_PATH_BULK_ALLOC, 0}}, > [ICE_RX_AVX512_SCATTERED_OFFLOAD] = { > - ice_recv_scattered_pkts_vec_avx512_offload, "Offload Vector AVX512 Scattered" }, > + ice_recv_scattered_pkts_vec_avx512_offload, "Offload Vector AVX512 Scattered", > + {ICE_RX_VECTOR_OFFLOAD_OFFLOADS, RTE_VECT_SIMD_512, > + CI_RX_PATH_SCATTERED, 0, CI_RX_PATH_BULK_ALLOC, 0}}, > #endif > #endif > }; > @@ -3694,89 +3712,51 @@ ice_set_rx_function(struct rte_eth_dev *dev) > PMD_INIT_FUNC_TRACE(); > struct ice_adapter *ad = > ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); > + enum rte_vect_max_simd rx_simd_width = RTE_VECT_SIMD_DISABLED; > + struct ci_rx_path_features req_features = { > + .rx_offloads = dev->data->dev_conf.rxmode.offloads, > + .simd_width = RTE_VECT_SIMD_DISABLED, > + }; > > /* The primary process selects the rx path for all processes. */ > if (rte_eal_process_type() != RTE_PROC_PRIMARY) > goto out; > > #ifdef RTE_ARCH_X86 > - struct ci_rx_queue *rxq; > - int i; > - int rx_check_ret = -1; > - enum rte_vect_max_simd rx_simd_width = RTE_VECT_SIMD_DISABLED; > - > - rx_check_ret = ice_rx_vec_dev_check(dev); > - if (ad->ptp_ena) > - rx_check_ret = -1; > - ad->rx_vec_offload_support = > - (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH); > - if (rx_check_ret >= 0 && ad->rx_bulk_alloc_allowed && > - rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { > - ad->rx_vec_allowed = true; > - for (i = 0; i < dev->data->nb_rx_queues; i++) { > - rxq = dev->data->rx_queues[i]; > - if (rxq && ice_rxq_vec_setup(rxq)) { > - ad->rx_vec_allowed = false; > - break; > - } > - } > - rx_simd_width = ice_get_max_simd_bitwidth(); > - > + if (ad->ptp_ena || !ad->rx_bulk_alloc_allowed) { > + rx_simd_width = RTE_VECT_SIMD_DISABLED; > } else { > - ad->rx_vec_allowed = false; > - } > - > - if (ad->rx_vec_allowed) { > - if (dev->data->scattered_rx) { > - if (rx_simd_width == RTE_VECT_SIMD_512) { > -#ifdef CC_AVX512_SUPPORT > - if (ad->rx_vec_offload_support) > - ad->rx_func_type = ICE_RX_AVX512_SCATTERED_OFFLOAD; > - else > - ad->rx_func_type = ICE_RX_AVX512_SCATTERED; > -#endif > - } else if (rx_simd_width == RTE_VECT_SIMD_256) { > - if (ad->rx_vec_offload_support) > - ad->rx_func_type = ICE_RX_AVX2_SCATTERED_OFFLOAD; > - else > - ad->rx_func_type = ICE_RX_AVX2_SCATTERED; > - } else { > - ad->rx_func_type = ICE_RX_SSE_SCATTERED; > - } > - } else { > - if (rx_simd_width == RTE_VECT_SIMD_512) { > -#ifdef CC_AVX512_SUPPORT > - if (ad->rx_vec_offload_support) > - ad->rx_func_type = ICE_RX_AVX512_OFFLOAD; > - else > - ad->rx_func_type = ICE_RX_AVX512; > -#endif > - } else if (rx_simd_width == RTE_VECT_SIMD_256) { > - if (ad->rx_vec_offload_support) > - ad->rx_func_type = ICE_RX_AVX2_OFFLOAD; > - else > - ad->rx_func_type = ICE_RX_AVX2; > - } else { > - ad->rx_func_type = ICE_RX_SSE; > - } > - } > - goto out; > + rx_simd_width = ice_get_max_simd_bitwidth(); > + if (rx_simd_width >= RTE_VECT_SIMD_128) > + if (ice_rx_vec_dev_check(dev) == -1) > + rx_simd_width = RTE_VECT_SIMD_DISABLED; > } > - > #endif > > + req_features.simd_width = rx_simd_width; > if (dev->data->scattered_rx) > - /* Set the non-LRO scattered function */ > - ad->rx_func_type = ICE_RX_SCATTERED; > - else if (ad->rx_bulk_alloc_allowed) > - ad->rx_func_type = ICE_RX_BULK_ALLOC; > - else > - ad->rx_func_type = ICE_RX_DEFAULT; > + req_features.scattered = CI_RX_PATH_SCATTERED; > + if (ad->rx_bulk_alloc_allowed) > + req_features.bulk_alloc = CI_RX_PATH_BULK_ALLOC; > + > + ad->rx_func_type = ci_rx_path_select(req_features, > + &ice_rx_path_infos[0], > + RTE_DIM(ice_rx_path_infos), > + ICE_RX_DEFAULT); > +#ifdef RTE_ARCH_X86 > + int i; > + > + if (ice_rx_path_infos[ad->rx_func_type].features.simd_width >= RTE_VECT_SIMD_128) > + /* Vector function selected. Prepare the rxq accordingly. */ > + for (i = 0; i < dev->data->nb_rx_queues; i++) > + if (dev->data->rx_queues[i]) > + ice_rxq_vec_setup(dev->data->rx_queues[i]); > +#endif > > out: > - dev->rx_pkt_burst = ice_rx_burst_infos[ad->rx_func_type].pkt_burst; > - PMD_DRV_LOG(NOTICE, "Using %s Rx burst function (port %d).", > - ice_rx_burst_infos[ad->rx_func_type].info, dev->data->port_id); > + dev->rx_pkt_burst = ice_rx_path_infos[ad->rx_func_type].pkt_burst; > + PMD_DRV_LOG(NOTICE, "Using %s (port %d).", > + ice_rx_path_infos[ad->rx_func_type].info, dev->data->port_id); > } > > int > @@ -3787,10 +3767,10 @@ ice_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, > int ret = -EINVAL; > unsigned int i; > > - for (i = 0; i < RTE_DIM(ice_rx_burst_infos); ++i) { > - if (pkt_burst == ice_rx_burst_infos[i].pkt_burst) { > + for (i = 0; i < RTE_DIM(ice_rx_path_infos); ++i) { > + if (pkt_burst == ice_rx_path_infos[i].pkt_burst) { > snprintf(mode->info, sizeof(mode->info), "%s", > - ice_rx_burst_infos[i].info); > + ice_rx_path_infos[i].info); > ret = 0; > break; > } > diff --git a/drivers/net/intel/ice/ice_rxtx.h b/drivers/net/intel/ice/ice_rxtx.h > index 8c3d6c413a..e6a18310a0 100644 > --- a/drivers/net/intel/ice/ice_rxtx.h > +++ b/drivers/net/intel/ice/ice_rxtx.h > @@ -80,6 +80,34 @@ > #define ICE_TX_OFFLOAD_NOTSUP_MASK \ > (RTE_MBUF_F_TX_OFFLOAD_MASK ^ ICE_TX_OFFLOAD_MASK) > > +#define ICE_RX_NO_OFFLOADS 0 > +/* basic scalar path */ > +#define ICE_RX_SCALAR_OFFLOADS ( \ > + RTE_ETH_RX_OFFLOAD_VLAN_STRIP | \ > + RTE_ETH_RX_OFFLOAD_KEEP_CRC | \ > + RTE_ETH_RX_OFFLOAD_SCATTER | \ > + RTE_ETH_RX_OFFLOAD_VLAN_FILTER | \ > + RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | \ > + RTE_ETH_RX_OFFLOAD_UDP_CKSUM | \ > + RTE_ETH_RX_OFFLOAD_TCP_CKSUM | \ > + RTE_ETH_RX_OFFLOAD_QINQ_STRIP | \ > + RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | \ > + RTE_ETH_RX_OFFLOAD_VLAN_EXTEND | \ > + RTE_ETH_RX_OFFLOAD_RSS_HASH | \ > + RTE_ETH_RX_OFFLOAD_TIMESTAMP | \ > + RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT) > +/* basic vector paths */ > +#define ICE_RX_VECTOR_OFFLOADS ( \ > + RTE_ETH_RX_OFFLOAD_KEEP_CRC | \ > + RTE_ETH_RX_OFFLOAD_SCATTER | \ > + RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM) > +/* vector offload paths */ > +#define ICE_RX_VECTOR_OFFLOAD_OFFLOADS ( \ > + ICE_RX_VECTOR_OFFLOADS | \ > + RTE_ETH_RX_OFFLOAD_CHECKSUM | \ > + RTE_ETH_RX_OFFLOAD_VLAN | \ The OFFLOAD_VLAN flag includes QINQ, which is not supported by the Rx vector path, so this needs to be replaced with OFFLOAD_VLAN_STRIP and OFFLOAD_VLAN_FILTER.