From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 30E824410E; Thu, 30 May 2024 13:14:59 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D3E0941060; Thu, 30 May 2024 13:14:33 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by mails.dpdk.org (Postfix) with ESMTP id 6F8A040ED3 for ; Thu, 30 May 2024 13:14:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717067671; x=1748603671; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BaBny1Z8ptqio0BlU3BiQ92uVV0ZoBM8AzX759r7Y3g=; b=HoMjBW2DrfBI/YJCEJV6zYkpSLH2uafc/5I/VOibhinCfkMouKPSSVDQ JDvsdkI2NfesRxpeb0tg5CslepflHKS3fx6nGAA6hyhJgQZ9J0RHZ4Gdh 8JtqTzmFgfuDAMGG8ZILWOtgl1LKDo1T8wQUD0g8dILUGwgXyTGR8Fa+p zakmqsbHNGTQXJdjw4UsiuywGg8iFkhWrrT5G1IcPpGBJJkxSM7wx0TJO RN+A1vsC8K9ENQrG4ipK2p8istvT6N2bUDJR9hQOFi8mEall/OpbOoil2 o5uWLcGUQWjCTFR6tKZBMuf032p9gC9GdcACu6nE4k5DaTByHeZfUb3xV w==; X-CSE-ConnectionGUID: HrQ00BRIRc6qTOsg6PUTdw== X-CSE-MsgGUID: rA47ltlQSX+DIALFHaPmxg== X-IronPort-AV: E=McAfee;i="6600,9927,11087"; a="36063610" X-IronPort-AV: E=Sophos;i="6.08,201,1712646000"; d="scan'208";a="36063610" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 May 2024 04:14:30 -0700 X-CSE-ConnectionGUID: 14yJuk2TR1u4TZY5dKGsZg== X-CSE-MsgGUID: ScEMd8/ST2mdXd5u4Yja4A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,201,1712646000"; d="scan'208";a="36419344" Received: from silpixa00401119.ir.intel.com ([10.55.129.167]) by orviesa007.jf.intel.com with ESMTP; 30 May 2024 04:14:27 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Jakub Chylkowski , vladimir.medvedkin@intel.com, bruce.richardson@intel.com, Zalfresso-jundzillo@dpdk.org, MarekX , Michael@dpdk.org, Alice , Skajewski@dpdk.org, PiotrX , Mrozowicz@dpdk.org, SlawomirX Subject: [PATCH v3 05/30] net/ixgbe/base: correct registers names to match datasheet Date: Thu, 30 May 2024 12:13:38 +0100 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Jakub Chylkowski Some of mailbox-related registers have different names than it is specified in datasheet. Correct these names to correspond to their datasheet counterparts. Additionally, several calculations are changed to no longer use magic numbers but dedicated macros instead. Signed-off-by: Jakub Chylkowski Reviewed-by: Zalfresso-jundzillo, MarekX Reviewed-by: Michael, Alice Reviewed-by: Skajewski, PiotrX Tested-by: Skajewski, PiotrX Reviewed-by: Mrozowicz, SlawomirX Tested-by: Michael, Alice --- drivers/net/ixgbe/base/ixgbe_mbx.c | 30 ++++++++++++++--------------- drivers/net/ixgbe/base/ixgbe_mbx.h | 8 ++++---- drivers/net/ixgbe/base/ixgbe_type.h | 12 ++++++------ 3 files changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/net/ixgbe/base/ixgbe_mbx.c b/drivers/net/ixgbe/base/ixgbe_mbx.c index 4dddff2c58..d645dcf827 100644 --- a/drivers/net/ixgbe/base/ixgbe_mbx.c +++ b/drivers/net/ixgbe/base/ixgbe_mbx.c @@ -496,12 +496,12 @@ void ixgbe_init_mbx_params_vf(struct ixgbe_hw *hw) STATIC s32 ixgbe_check_for_bit_pf(struct ixgbe_hw *hw, u32 mask, s32 index) { - u32 mbvficr = IXGBE_READ_REG(hw, IXGBE_MBVFICR(index)); + u32 pfmbicr = IXGBE_READ_REG(hw, IXGBE_PFMBICR(index)); s32 ret_val = IXGBE_ERR_MBX; - if (mbvficr & mask) { + if (pfmbicr & mask) { ret_val = IXGBE_SUCCESS; - IXGBE_WRITE_REG(hw, IXGBE_MBVFICR(index), mask); + IXGBE_WRITE_REG(hw, IXGBE_PFMBICR(index), mask); } return ret_val; @@ -516,13 +516,13 @@ STATIC s32 ixgbe_check_for_bit_pf(struct ixgbe_hw *hw, u32 mask, s32 index) **/ STATIC s32 ixgbe_check_for_msg_pf(struct ixgbe_hw *hw, u16 vf_number) { + u32 vf_shift = IXGBE_PFMBICR_SHIFT(vf_number); + s32 index = IXGBE_PFMBICR_INDEX(vf_number); s32 ret_val = IXGBE_ERR_MBX; - s32 index = IXGBE_MBVFICR_INDEX(vf_number); - u32 vf_bit = vf_number % 16; DEBUGFUNC("ixgbe_check_for_msg_pf"); - if (!ixgbe_check_for_bit_pf(hw, IXGBE_MBVFICR_VFREQ_VF1 << vf_bit, + if (!ixgbe_check_for_bit_pf(hw, IXGBE_PFMBICR_VFREQ_VF1 << vf_shift, index)) { ret_val = IXGBE_SUCCESS; hw->mbx.stats.reqs++; @@ -540,13 +540,13 @@ STATIC s32 ixgbe_check_for_msg_pf(struct ixgbe_hw *hw, u16 vf_number) **/ STATIC s32 ixgbe_check_for_ack_pf(struct ixgbe_hw *hw, u16 vf_number) { + u32 vf_shift = IXGBE_PFMBICR_SHIFT(vf_number); + s32 index = IXGBE_PFMBICR_INDEX(vf_number); s32 ret_val = IXGBE_ERR_MBX; - s32 index = IXGBE_MBVFICR_INDEX(vf_number); - u32 vf_bit = vf_number % 16; DEBUGFUNC("ixgbe_check_for_ack_pf"); - if (!ixgbe_check_for_bit_pf(hw, IXGBE_MBVFICR_VFACK_VF1 << vf_bit, + if (!ixgbe_check_for_bit_pf(hw, IXGBE_PFMBICR_VFACK_VF1 << vf_shift, index)) { ret_val = IXGBE_SUCCESS; hw->mbx.stats.acks++; @@ -564,22 +564,22 @@ STATIC s32 ixgbe_check_for_ack_pf(struct ixgbe_hw *hw, u16 vf_number) **/ STATIC s32 ixgbe_check_for_rst_pf(struct ixgbe_hw *hw, u16 vf_number) { - u32 reg_offset = (vf_number < 32) ? 0 : 1; - u32 vf_shift = vf_number % 32; + u32 vf_shift = IXGBE_PFVFLRE_SHIFT(vf_number); + u32 index = IXGBE_PFVFLRE_INDEX(vf_number); + s32 ret_val = IXGBE_ERR_MBX; u32 vflre = 0; - s32 ret_val = IXGBE_ERR_MBX; DEBUGFUNC("ixgbe_check_for_rst_pf"); switch (hw->mac.type) { case ixgbe_mac_82599EB: - vflre = IXGBE_READ_REG(hw, IXGBE_VFLRE(reg_offset)); + vflre = IXGBE_READ_REG(hw, IXGBE_PFVFLRE(index)); break; case ixgbe_mac_X550: case ixgbe_mac_X550EM_x: case ixgbe_mac_X550EM_a: case ixgbe_mac_X540: - vflre = IXGBE_READ_REG(hw, IXGBE_VFLREC(reg_offset)); + vflre = IXGBE_READ_REG(hw, IXGBE_PFVFLREC(index)); break; default: break; @@ -587,7 +587,7 @@ STATIC s32 ixgbe_check_for_rst_pf(struct ixgbe_hw *hw, u16 vf_number) if (vflre & (1 << vf_shift)) { ret_val = IXGBE_SUCCESS; - IXGBE_WRITE_REG(hw, IXGBE_VFLREC(reg_offset), (1 << vf_shift)); + IXGBE_WRITE_REG(hw, IXGBE_PFVFLREC(index), (1 << vf_shift)); hw->mbx.stats.rsts++; } diff --git a/drivers/net/ixgbe/base/ixgbe_mbx.h b/drivers/net/ixgbe/base/ixgbe_mbx.h index 28a2d94d02..f7861e6bde 100644 --- a/drivers/net/ixgbe/base/ixgbe_mbx.h +++ b/drivers/net/ixgbe/base/ixgbe_mbx.h @@ -30,10 +30,10 @@ #define IXGBE_PFMAILBOX_PFU 0x00000008 /* PF owns the mailbox buffer */ #define IXGBE_PFMAILBOX_RVFU 0x00000010 /* Reset VFU - used when VF stuck */ -#define IXGBE_MBVFICR_VFREQ_MASK 0x0000FFFF /* bits for VF messages */ -#define IXGBE_MBVFICR_VFREQ_VF1 0x00000001 /* bit for VF 1 message */ -#define IXGBE_MBVFICR_VFACK_MASK 0xFFFF0000 /* bits for VF acks */ -#define IXGBE_MBVFICR_VFACK_VF1 0x00010000 /* bit for VF 1 ack */ +#define IXGBE_PFMBICR_VFREQ_MASK 0x0000FFFF /* bits for VF messages */ +#define IXGBE_PFMBICR_VFREQ_VF1 0x00000001 /* bit for VF 1 message */ +#define IXGBE_PFMBICR_VFACK_MASK 0xFFFF0000 /* bits for VF acks */ +#define IXGBE_PFMBICR_VFACK_VF1 0x00010000 /* bit for VF 1 ack */ /* If it's a IXGBE_VF_* msg then it originates in the VF and is sent to the diff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h index f709681df2..5036b2a907 100644 --- a/drivers/net/ixgbe/base/ixgbe_type.h +++ b/drivers/net/ixgbe/base/ixgbe_type.h @@ -451,8 +451,14 @@ struct ixgbe_nvm_version { #define IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i))) /* 64 total */ /* 64 Mailboxes, 16 DW each */ #define IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i))) +#define IXGBE_PFMBICR_INDEX(_i) ((_i) >> 4) +#define IXGBE_PFMBICR_SHIFT(_i) ((_i) % 16) #define IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i))) /* 4 total */ #define IXGBE_PFMBIMR(_i) (0x00720 + (4 * (_i))) /* 4 total */ +#define IXGBE_PFVFLRE(_i) ((((_i) & 1) ? 0x001C0 : 0x00600)) +#define IXGBE_PFVFLREC(_i) (0x00700 + ((_i) * 4)) +#define IXGBE_PFVFLRE_INDEX(_i) ((_i) >> 5) +#define IXGBE_PFVFLRE_SHIFT(_i) ((_i) % 32) #define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4)) #define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4)) #define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4)) @@ -2866,12 +2872,6 @@ enum { #define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */ #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */ #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT - -/* SR-IOV specific macros */ -#define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4) -#define IXGBE_MBVFICR(_i) (0x00710 + ((_i) * 4)) -#define IXGBE_VFLRE(_i) (((_i & 1) ? 0x001C0 : 0x00600)) -#define IXGBE_VFLREC(_i) (0x00700 + ((_i) * 4)) /* Translated register #defines */ #define IXGBE_PVFCTRL(P) (0x00300 + (4 * (P))) #define IXGBE_PVFSTATUS(P) (0x00008 + (0 * (P))) -- 2.43.0