From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf0-f182.google.com (mail-pf0-f182.google.com [209.85.192.182]) by dpdk.org (Postfix) with ESMTP id 8A3A11B2EB for ; Wed, 8 Nov 2017 16:11:50 +0100 (CET) Received: by mail-pf0-f182.google.com with SMTP id a8so1934394pfc.0 for ; Wed, 08 Nov 2017 07:11:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-transfer-encoding; bh=B8H2VacoaTQItX+dx69gJC3BuQ2zHPdlhVMdfkM5Oi4=; b=nRjwPVuJBM6o0PMRtvZGftEUlhQRaqPOQJ6WwXIDmslsuLKj8Hk4OdOtZmZGrXIQeZ 0tWPdpP7aQecmdKKFdkIDucsaT+GGP1ni6Zv+PxlU6V2UOw4wVook4rg9xlhUuYt0QIF rDG0N6pg69YFMKoVtYy2smshSm+M1sLW6+rOIsuS9yOURfyh8Lw1AgKdcHqXrnf1C3qN fYCcjiPIzxv0lzLBCdDi1yxvNqVxDHaXjbdRbCWz8D9eto28uMiImEXVYaIayOltPRxq KvdHmHFCqc5U6t20Ywpl54/iVDrzlZCG00Xv/1h2en1ZyZErDWRlYdj3ELhLoVl1OkM0 BL1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-transfer-encoding; bh=B8H2VacoaTQItX+dx69gJC3BuQ2zHPdlhVMdfkM5Oi4=; b=jW5xl0PudQhW3K4E7IEpe547+EZnho04vkNtqkm5rZLBFNirVQsK5wV1DrrWnJt01d EgqlaPCbzrP39ptvO1CcIBI8TMuo3mpcIEsKlIbmDt5QnAVci/sdo4M8tPz4jt6o5Tdd FzO05RBNMd/zF43SUw+y9hkplmE8Un3SOJJgjfSmOri0wrFVVrFpgRy6HKPQJbN9oA+Z qOaj7POhtZdQRDLAaddg+wCky04e9Upgk3rjn356A7sz3NYeuXRYewrpi1JLVKskm58Z JtFq35Pz+qYOlmLR2OTfKxGJ6QK8pgTRhZQ9NhbvHjn6qJ97PJVs3VhRxxJAtx1+g6kK 1IcQ== X-Gm-Message-State: AJaThX7fnM1ART/IQoosIbcyCOBR0wMuLP4gmXefA3fUnAts7/VHGD3t zS11dfqDKXkHJjvXTkuroB0= X-Google-Smtp-Source: ABhQp+RdvwZaTKLPm9CNZhWf5dURq0/TdrRIjVpT1oHsCqEnTUIZkLksYJpSko1pV7TB6L6XnhByRw== X-Received: by 10.99.121.201 with SMTP id u192mr772751pgc.69.1510153909650; Wed, 08 Nov 2017 07:11:49 -0800 (PST) Received: from [0.0.0.0] (67.209.179.165.16clouds.com. [67.209.179.165]) by smtp.gmail.com with ESMTPSA id h1sm8393742pfg.143.2017.11.08.07.11.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 08 Nov 2017 07:11:48 -0800 (PST) To: Bruce Richardson Cc: jerin.jacob@caviumnetworks.com, dev@dpdk.org, olivier.matz@6wind.com, konstantin.ananyev@intel.com, jianbo.liu@arm.com, hemant.agrawal@nxp.com References: <1510118764-29697-1-git-send-email-hejianet@gmail.com> <1510134881-22987-1-git-send-email-hejianet@gmail.com> <20171108121550.GA9632@bricha3-MOBL3.ger.corp.intel.com> From: Jia He Message-ID: Date: Wed, 8 Nov 2017 23:11:32 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 MIME-Version: 1.0 In-Reply-To: <20171108121550.GA9632@bricha3-MOBL3.ger.corp.intel.com> Content-Type: text/plain; charset=gbk; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [dpdk-dev] [PATCH v4 0/4] fix race condition in enqueue/dequeue because of cpu reorder X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 08 Nov 2017 15:11:50 -0000 Hi Bruce On 11/8/2017 8:15 PM, Bruce Richardson Wrote: > On Wed, Nov 08, 2017 at 09:54:37AM +0000, Jia He wrote: >> We watched a rte panic of mbuf_autotest in our qualcomm arm64 server >> due to a possible race condition. >> >> To fix this race, there are 2 options as suggested by Jerin: 1. use >> rte_smp_rmb 2. use load_acquire/store_release(refer to [2]). >> CONFIG_RTE_RING_USE_C11_MEM_MODEL is provided, and by default it is >> "y" only on arm64 so far. >> >> The reason why providing 2 options is due to the performance benchmark >> difference in different arm machines. >> >> Already fuctionally tested on the machines as follows: - on X86 - on >> arm64 with CONFIG_RTE_RING_USE_C11_MEM_MODEL=y - on arm64 with >> CONFIG_RTE_RING_USE_C11_MEM_MODEL=n >> >> --- Changelog: V4: split into small patches V3: arch specific >> implementation for enqueue/dequeue barrier V2: let users choose >> whether using load_acquire/store_release V1: rte_smp_rmb() between 2 >> loads >> >> Jia He (4): eal/arm64: remove the braces {} for dmb() and dsb() ring: >> guarantee load/load order in enqueue and dequeue ring: introduce new >> header file to include common functions ring: introduce new header >> file to support C11 memory model >> > I'm wondering what the merge plans are for this set, given we are now > past RC3 in 17.11? As the rings are broken on ARM machines we need to > merge in some fix, but I'm a little concerned about the scope of the > changes from the 3rd and 4th patches. Would it be acceptable to just > merge in patches 1 & 2 in 17.11 and leave the rework and C11 memory > model additions in patches 3 & 4 to 18.02 release? As far as I'm concerned, it is ok. Cheers, Jia