From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [148.163.129.52]) by dpdk.org (Postfix) with ESMTP id 9214CA49C for ; Tue, 16 Jan 2018 08:49:18 +0100 (CET) X-Virus-Scanned: Proofpoint Essentials engine Received: from webmail.solarflare.com (uk.solarflare.com [193.34.186.16]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1-us1.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with ESMTPS id D9EFB100059; Tue, 16 Jan 2018 07:49:16 +0000 (UTC) Received: from [192.168.38.17] (84.52.114.114) by ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Tue, 16 Jan 2018 07:49:10 +0000 To: Yongseok Koh , , , , CC: References: <20171227042824.33373-1-yskoh@mellanox.com> <20180116011050.18866-1-yskoh@mellanox.com> <20180116011050.18866-2-yskoh@mellanox.com> From: Andrew Rybchenko Message-ID: Date: Tue, 16 Jan 2018 10:49:06 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.2 MIME-Version: 1.0 In-Reply-To: <20180116011050.18866-2-yskoh@mellanox.com> Content-Language: en-GB X-Originating-IP: [84.52.114.114] X-ClientProxiedBy: ocex03.SolarFlarecom.com (10.20.40.36) To ukex01.SolarFlarecom.com (10.17.10.4) X-TM-AS-Product-Ver: SMEX-11.0.0.1191-8.100.1062-23598.003 X-TM-AS-Result: No--11.109600-0.000000-31 X-TM-AS-User-Approved-Sender: Yes X-TM-AS-User-Blocked-Sender: No X-MDID: 1516088958-gNg0vNx55ieN Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Subject: Re: [dpdk-dev] [PATCH v2 1/8] eal: introduce DMA memory barriers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 16 Jan 2018 07:49:19 -0000 On 01/16/2018 04:10 AM, Yongseok Koh wrote: > This commit introduces rte_dma_wmb() and rte_dma_rmb(), in order to > guarantee the ordering of coherent shared memory between the CPU and a DMA > capable device. > > Signed-off-by: Yongseok Koh > --- > lib/librte_eal/common/include/generic/rte_atomic.h | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/lib/librte_eal/common/include/generic/rte_atomic.h b/lib/librte_eal/common/include/generic/rte_atomic.h > index 16af5ca57..2e0503ce6 100644 > --- a/lib/librte_eal/common/include/generic/rte_atomic.h > +++ b/lib/librte_eal/common/include/generic/rte_atomic.h > @@ -98,6 +98,24 @@ static inline void rte_io_wmb(void); > */ > static inline void rte_io_rmb(void); > > +/** > + * Write memory barrier for coherent memory between lcore and IO device > + * > + * Guarantees that the STORE operations on coherent memory that > + * precede the rte_dma_wmb() call are visible to I/O device before the > + * STORE operations that follow it. > + */ > +static inline void rte_dma_wmb(void); > + > +/** > + * Read memory barrier for coherent memory between lcore and IO device > + * > + * Guarantees that the LOAD operations on coherent memory updated by > + * IO device that precede the rte_dma_rmb() call are visible to CPU > + * before the LOAD operations that follow it. > + */ > +static inline void rte_dma_rmb(void); > + > #endif /* __DOXYGEN__ */ > > /** I'm not an ARMv8 expert so, my comments could be a bit ignorant. I'd like to understand the difference between io and added here dma barriers. The difference should be clearly explained. Otherwise we'll constantly hit on incorrect choice of barrier type. Also I don't understand why "dma" name is chosen taking into account that definition is bound to coherent memory between lcore and IO device.