From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 70F0BA034F; Mon, 22 Feb 2021 18:26:01 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 060B840041; Mon, 22 Feb 2021 18:26:01 +0100 (CET) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id EB4FF4003C for ; Mon, 22 Feb 2021 18:25:58 +0100 (CET) IronPort-SDR: WABvBoTnvnpvcAPXD7uk7q/rpo2vOJeGRmouK6bIRHWllX3Fn+MjsxRBRnGiiYTTk3mB2fhxMD k459hCiWRfSQ== X-IronPort-AV: E=McAfee;i="6000,8403,9903"; a="164361647" X-IronPort-AV: E=Sophos;i="5.81,197,1610438400"; d="scan'208";a="164361647" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Feb 2021 09:25:57 -0800 IronPort-SDR: TmnWdcPIy2dSRZ944dyvpBZZSOdb/zCR5i3FeIFCPwhapMtd02gDBbkUh4L9P8DuSEYg+ZgwDb PQwEmMTomyTw== X-IronPort-AV: E=Sophos;i="5.81,197,1610438400"; d="scan'208";a="498636506" Received: from fyigit-mobl1.ger.corp.intel.com (HELO [10.213.216.168]) ([10.213.216.168]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Feb 2021 09:25:55 -0800 To: =?UTF-8?B?6LCi5Y2O5LyfKOatpOaXtuatpOWIu++8iQ==?= , maxime.coquelin@redhat.com, david.marchand@redhat.com Cc: dev@dpdk.org, anatoly.burakov@intel.com, xuemingl@nvidia.com, grive@u256.net, chenbo.xia@intel.com References: <1611890309-99135-1-git-send-email-huawei.xhw@alibaba-inc.com> <1614014118-91150-1-git-send-email-huawei.xhw@alibaba-inc.com> <1614014118-91150-3-git-send-email-huawei.xhw@alibaba-inc.com> From: Ferruh Yigit X-User: ferruhy Message-ID: Date: Mon, 22 Feb 2021 17:25:52 +0000 MIME-Version: 1.0 In-Reply-To: <1614014118-91150-3-git-send-email-huawei.xhw@alibaba-inc.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH v7 2/2] bus/pci: support MMIO in PCI ioport accessors X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 2/22/2021 5:15 PM, 谢华伟(此时此刻） wrote: > From: "huawei.xhw" > > With IO BAR, we get PIO(programmed IO) address. > With MMIO BAR, we get mapped virtual address. > We distinguish PIO(Programmed IO) and MMIO(memory mapped IO) by their address like how kernel does. > ioread/write8/16/32 is provided to access PIO/MMIO. > By the way, for virtio on arch other than x86, BAR flag indicates PIO but is mapped. > > Signed-off-by: huawei xie > Reviewed-by: Maxime Coquelin <...> > + > +static inline void iowrite8(uint8_t val, void *addr) > +{ > + (uint64_t)(uintptr_t)addr >= PIO_MAX ? > + *(volatile uint8_t *)addr = val : > + outb(val, (unsigned long)addr); //copying question from previous version: Is the 'outb_p' to 'outb' conversion intentional? And if so why? Same of the all 'outb_p', 'outw_p', 'outl_p'.