From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from stargate3.asicdesigners.com (stargate.chelsio.com [67.207.112.58]) by dpdk.org (Postfix) with ESMTP id CECD1C3CC for ; Mon, 20 Jul 2015 08:41:50 +0200 (CEST) Received: from localhost (scalar.blr.asicdesigners.com [10.193.185.94]) by stargate3.asicdesigners.com (8.13.8/8.13.8) with ESMTP id t6K6fhbZ026718; Sun, 19 Jul 2015 23:41:43 -0700 From: Rahul Lakkireddy To: dev@dpdk.org Date: Mon, 20 Jul 2015 12:11:12 +0530 Message-Id: X-Mailer: git-send-email 2.4.1 In-Reply-To: References: In-Reply-To: References: Cc: Felix Marti , Kumar Sanghvi , Nirranjan Kirubaharan Subject: [dpdk-dev] [PATCH v2 2/3] cxgbe: Enable and fix FreeBSD compilation for CXGBE PMD X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 20 Jul 2015 06:41:51 -0000 Fix "MACRO redefined" and "function redefined" compilation errors in FreeBSD by adding CXGBE prefix to them. Also remove reference to a linux header linux/if_ether.h and use DPDK macros directly. Finally, enable CXGBE PMD for FreeBSD. Signed-off-by: Rahul Lakkireddy Signed-off-by: Kumar Sanghvi --- v2: - No changes. config/common_bsdapp | 2 +- drivers/net/cxgbe/base/common.h | 2 +- drivers/net/cxgbe/base/t4_hw.c | 6 +++--- drivers/net/cxgbe/cxgbe_compat.h | 12 ++++++------ drivers/net/cxgbe/cxgbe_main.c | 4 ++-- drivers/net/cxgbe/sge.c | 10 +++++----- 6 files changed, 18 insertions(+), 18 deletions(-) diff --git a/config/common_bsdapp b/config/common_bsdapp index 4e505bf..e96e4a5 100644 --- a/config/common_bsdapp +++ b/config/common_bsdapp @@ -217,7 +217,7 @@ CONFIG_RTE_LIBRTE_MLX4_SOFT_COUNTERS=1 # # Compile burst-oriented Chelsio Terminator 10GbE/40GbE (CXGBE) PMD # -CONFIG_RTE_LIBRTE_CXGBE_PMD=n +CONFIG_RTE_LIBRTE_CXGBE_PMD=y CONFIG_RTE_LIBRTE_CXGBE_DEBUG=n CONFIG_RTE_LIBRTE_CXGBE_DEBUG_REG=n CONFIG_RTE_LIBRTE_CXGBE_DEBUG_MBOX=n diff --git a/drivers/net/cxgbe/base/common.h b/drivers/net/cxgbe/base/common.h index 6ddc7d4..cf2e82d 100644 --- a/drivers/net/cxgbe/base/common.h +++ b/drivers/net/cxgbe/base/common.h @@ -43,7 +43,7 @@ extern "C" { #endif -#define PAGE_SIZE RTE_PGSIZE_4K +#define CXGBE_PAGE_SIZE RTE_PGSIZE_4K enum { MAX_NPORTS = 4, /* max # of ports */ diff --git a/drivers/net/cxgbe/base/t4_hw.c b/drivers/net/cxgbe/base/t4_hw.c index c57200e..884d2cf 100644 --- a/drivers/net/cxgbe/base/t4_hw.c +++ b/drivers/net/cxgbe/base/t4_hw.c @@ -127,7 +127,7 @@ void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, for (i = 0; i < NMTUS; ++i) { unsigned int mtu = mtus[i]; - unsigned int log2 = fls(mtu); + unsigned int log2 = cxgbe_fls(mtu); if (!(mtu & ((1 << log2) >> 2))) /* round */ log2--; @@ -1545,11 +1545,11 @@ int t4_fixup_host_params_compat(struct adapter *adap, unsigned int cache_line_size, enum chip_type chip_compat) { - unsigned int page_shift = fls(page_size) - 1; + unsigned int page_shift = cxgbe_fls(page_size) - 1; unsigned int sge_hps = page_shift - 10; unsigned int stat_len = cache_line_size > 64 ? 128 : 64; unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size; - unsigned int fl_align_log = fls(fl_align) - 1; + unsigned int fl_align_log = cxgbe_fls(fl_align) - 1; t4_write_reg(adap, A_SGE_HOST_PAGE_SIZE, V_HOSTPAGESIZEPF0(sge_hps) | diff --git a/drivers/net/cxgbe/cxgbe_compat.h b/drivers/net/cxgbe/cxgbe_compat.h index 3b871ee..e68f8f5 100644 --- a/drivers/net/cxgbe/cxgbe_compat.h +++ b/drivers/net/cxgbe/cxgbe_compat.h @@ -119,8 +119,8 @@ #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) #define PAGE_SHIFT 12 -#define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) -#define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a))) +#define CXGBE_ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) +#define PTR_ALIGN(p, a) ((typeof(p))CXGBE_ALIGN((unsigned long)(p), (a))) #define VLAN_HLEN 4 @@ -178,7 +178,7 @@ typedef uint64_t dma_addr_t; /* * round up val _p to a power of 2 size _s */ -#define roundup(_p, _s) (((unsigned long)(_p) + (_s - 1)) & ~(_s - 1)) +#define cxgbe_roundup(_p, _s) (((unsigned long)(_p) + (_s - 1)) & ~(_s - 1)) #undef container_of #define container_of(ptr, type, member) ({ \ @@ -214,13 +214,13 @@ static inline uint8_t hweight32(uint32_t word32) } /* weight32 */ /** - * fls - find last (most-significant) bit set + * cxgbe_fls - find last (most-significant) bit set * @x: the word to search * * This is defined the same way as ffs. - * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. + * Note cxgbe_fls(0) = 0, cxgbe_fls(1) = 1, cxgbe_fls(0x80000000) = 32. */ -static inline int fls(int x) +static inline int cxgbe_fls(int x) { return x ? sizeof(x) * 8 - __builtin_clz(x) : 0; } diff --git a/drivers/net/cxgbe/cxgbe_main.c b/drivers/net/cxgbe/cxgbe_main.c index b879820..3755444 100644 --- a/drivers/net/cxgbe/cxgbe_main.c +++ b/drivers/net/cxgbe/cxgbe_main.c @@ -411,7 +411,7 @@ static int adap_init0_tweaks(struct adapter *adapter) * Line Size, etc. The firmware default is for a 4KB Page Size and * 64B Cache Line Size ... */ - t4_fixup_host_params_compat(adapter, PAGE_SIZE, L1_CACHE_BYTES, + t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES, T5_LAST_REV); /* @@ -1100,7 +1100,7 @@ int cxgbe_probe(struct adapter *adapter) qpp = 1 << ((t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp) & M_QUEUESPERPAGEPF0); - num_seg = PAGE_SIZE / UDBS_SEG_SIZE; + num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE; if (qpp > num_seg) dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n"); diff --git a/drivers/net/cxgbe/sge.c b/drivers/net/cxgbe/sge.c index 1a10278..d570d33 100644 --- a/drivers/net/cxgbe/sge.c +++ b/drivers/net/cxgbe/sge.c @@ -31,7 +31,6 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include #include #include #include @@ -98,7 +97,8 @@ static inline unsigned int fl_mtu_bufsize(struct adapter *adapter, { struct sge *s = &adapter->sge; - return ALIGN(s->pktshift + ETH_HLEN + VLAN_HLEN + mtu, s->fl_align); + return CXGBE_ALIGN(s->pktshift + ETHER_HDR_LEN + VLAN_HLEN + mtu, + s->fl_align); } #define FL_MTU_SMALL_BUFSIZE(adapter) fl_mtu_bufsize(adapter, FL_MTU_SMALL) @@ -1578,7 +1578,7 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, unsigned int nb_refill; /* Size needs to be multiple of 16, including status entry. */ - iq->size = roundup(iq->size, 16); + iq->size = cxgbe_roundup(iq->size, 16); snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d", eth_dev->driver->pci_drv.name, fwevtq ? "fwq_ring" : "rx_ring", @@ -1630,7 +1630,7 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, */ if (fl->size < s->fl_starve_thres - 1 + 2 * 8) fl->size = s->fl_starve_thres - 1 + 2 * 8; - fl->size = roundup(fl->size, 8); + fl->size = cxgbe_roundup(fl->size, 8); snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d", eth_dev->driver->pci_drv.name, @@ -2064,7 +2064,7 @@ static int t4_sge_init_soft(struct adapter *adap) * The Page Size Buffer must be exactly equal to our Page Size and the * Large Page Size Buffer should be 0 (per above) or a power of 2. */ - if (fl_small_pg != PAGE_SIZE || + if (fl_small_pg != CXGBE_PAGE_SIZE || (fl_large_pg & (fl_large_pg - 1)) != 0) { dev_err(adap, "bad SGE FL page buffer sizes [%d, %d]\n", fl_small_pg, fl_large_pg); -- 2.4.1