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dmarc=fail action=none header.from=nxp.com; Received-SPF: Fail (protection.outlook.com: domain of nxp.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Received: from tx30smr01.am.freescale.net (192.88.168.50) by BY2FFO11FD043.mail.protection.outlook.com (10.1.14.228) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.35.14 via Frontend Transport; Fri, 22 Sep 2017 12:55:09 +0000 Received: from [10.232.14.39] ([10.232.14.39]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id v8MCt7Ae018919; Fri, 22 Sep 2017 05:55:07 -0700 To: Thomas Monjalon CC: , , References: <20170823141213.25476-1-shreyansh.jain@nxp.com> <20170909112132.13936-1-shreyansh.jain@nxp.com> <25531756.sobbYYJFMz@xps> From: Shreyansh Jain Message-ID: Date: Fri, 22 Sep 2017 18:36:03 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: <25531756.sobbYYJFMz@xps> Content-Type: text/plain; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO2PR03MB2360 Subject: Re: [dpdk-dev] [PATCH v4 00/41] Introduce NXP DPAA Bus, Mempool and PMD X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Sep 2017 12:55:12 -0000 On Friday 22 September 2017 03:40 AM, Thomas Monjalon wrote: > 09/09/2017 13:20, Shreyansh Jain: >> DPAA, or Datapath Acceleration Architecture [R2], is a set of hardware >> components designed for high-speed network packet processing. This >> architecture provides the infrastructure to support simplified sharing of >> networking interfaces and accelerators by multiple CPU cores, and the >> accelerators themselves. >> >> This patchset introduces the following: >> 1. DPAA Bus (drivers/bus/dpaa) >> The core of DPAA bus is implemented using 3 main hardware blocks: QMan, >> or Queue Manager; BMan, or Buffer Manager and FMan, or Frame Manager. >> The patches introduce necessary layers to expose the DPAA hardware >> blocks for interfacing with RTE framework. > > I guess these are the same blocks as for DPAA2? > They are in drivers/bus/fslmc/ > Why introducing yet another bus driver? > The fslmc one was supposed to cover any Freescale (NXP (Qualcomm)) SoC. Forgot to reply to this in previous email: No, fslmc is not compatible with DPAA. They are completely different architectures. I am not sure why you have the notion "fslmc one was supposed to cover any Freescale (NXP (Qualcomm)) SoC". That is not correct - FSLMC was always for supporting DPAA2 which is based on VFIO. DPAA is more closer to a platform layout. And I don't think we should have single "bus/fslmc" just so that it can encompass all NXP SoC. I am assuming you didn't mean this :P. > >> 2. DPAA Mempool (drivers/mempool/dpaa) >> BMan, or Buffer Manager, block of DPAA features a hardware offloaded >> mempool. These patches add support for a driver to manage the BMan >> block. This driver allows for mempool creation, deletion, buffer >> acquire and release, as per the RTE APIs. >> >> 3. DPAA PMD (drivers/net/dpaa) >> The Poll Mode Driver for DPAA NIC Interfaces. >> >> Patch Layout >> ============ >> >> 01: Add DPAA SoC build configuration >> 02~16: Add DPAA Bus support and features, incrementally >> 17: Add Documentation >> 18~21: Add DPAA Mempool support >> 22~41: Add PMD and its various features, incrementally > > It is a very long series introducing 3 different subsystems. > I think everybody was scared about reviewing it. > Why you did not split it? > >