From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 56D454404F; Wed, 12 Jun 2024 17:19:37 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5E6AC42ED8; Wed, 12 Jun 2024 17:06:06 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mails.dpdk.org (Postfix) with ESMTP id A697E42F51 for ; Wed, 12 Jun 2024 17:06:02 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718204765; x=1749740765; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=drFwBkzTXeNzxkU0jA/pQ0EK9ylyhpxvlXfFCqJ/n8E=; b=PpKvl1i001mcdcBxzTKdtK8uUPNMMq1oxqTJg5nUj9aPeQjba00y2N8S cJ+KHiRLog80OKqoamg6xkwHVzRJhS3E8/uTL1L0sLPMdlJUjI40rUaBN WKHXd4p9Vw5jzm0tgbWwqzcE0cJYF9hXaM5QUKWdnp+X7/ZRcXn6uXFLg l47Ud9y0few7BGqpNHGmWgeIv1GGezbKSxGrpYdKVTQLBbhOK6er1Vu1M xJRpKZsCHXn9dbkVzafT/GXR9q0mzj0zoS6O9BT3qfFjFzK0yr2UDxA4v YfjWecmKM/2XTWzknLN501ZUKhc1SVaDGuPeQVa752u1deL4vs3M4pOvO Q==; X-CSE-ConnectionGUID: qkBMbli3TqOssAjUemlDWg== X-CSE-MsgGUID: XVoQ5KEMR2a1x6dYn6EqBA== X-IronPort-AV: E=McAfee;i="6700,10204,11101"; a="32459841" X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="32459841" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2024 08:06:02 -0700 X-CSE-ConnectionGUID: jWWLG7uCRX2QAKjg98pJ2w== X-CSE-MsgGUID: WCvLv7iaQr2f6cvOiQ14xw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="39925771" Received: from silpixa00401119.ir.intel.com ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 12 Jun 2024 08:06:00 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Ian Stokes , bruce.richardson@intel.com, Karol Kolacinski Subject: [PATCH v2 100/148] net/ice/base: add PHY OFFSET_READY register clearing Date: Wed, 12 Jun 2024 16:01:34 +0100 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: <20240430154014.1026-1-ian.stokes@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Ian Stokes Add a possibility to mark all transmitted/received timestamps as invalid by clearing PHY OFFSET_READY registers. Signed-off-by: Karol Kolacinski Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_ptp_hw.c | 84 +++++++++++++++++++++++++++++++ drivers/net/ice/base/ice_ptp_hw.h | 1 + 2 files changed, 85 insertions(+) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 52a6178fd4..137f926c94 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -1981,6 +1981,38 @@ int ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port) return ice_write_phy_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 1); } +/** + * ice_ptp_clear_phy_offset_ready_eth56g - Clear PHY OFFSET_READY registers + * @hw: pointer to the HW struct + * + * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted + * and received timestamps as invalid. + */ +static int ice_ptp_clear_phy_offset_ready_eth56g(struct ice_hw *hw) +{ + u8 port; + + for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + int err; + + err = ice_write_phy_reg_eth56g(hw, port, + PHY_REG_TX_OFFSET_READY, 0); + if (err) { + ice_warn(hw, "Failed to clear PHY TX_OFFSET_READY register\n"); + return err; + } + + err = ice_write_phy_reg_eth56g(hw, port, + PHY_REG_RX_OFFSET_READY, 0); + if (err) { + ice_warn(hw, "Failed to clear PHY RX_OFFSET_READY register\n"); + return err; + } + } + + return 0; +} + /** * ice_read_phy_and_phc_time_eth56g - Simultaneously capture PHC and PHY time * @hw: pointer to the HW struct @@ -4068,6 +4100,36 @@ int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port) return 0; } +/** + * ice_ptp_clear_phy_offset_ready_e822 - Clear PHY TX_/RX_OFFSET_READY registers + * @hw: pointer to the HW struct + * + * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted + * and received timestamps as invalid. + */ +static int ice_ptp_clear_phy_offset_ready_e822(struct ice_hw *hw) +{ + u8 port; + + for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { + int err; + + err = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 0); + if (err) { + ice_warn(hw, "Failed to clear PHY TX_OFFSET_READY register\n"); + return err; + } + + err = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 0); + if (err) { + ice_warn(hw, "Failed to clear PHY RX_OFFSET_READY register\n"); + return err; + } + } + + return 0; +} + /** * ice_phy_cfg_fixed_rx_offset_e822 - Configure fixed Rx offset for bypass mode * @hw: pointer to the HW struct @@ -5801,6 +5863,28 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj) return ice_ptp_tmr_cmd(hw, ICE_PTP_ADJ_TIME_AT_TIME, true); } +/** + * ice_ptp_clear_phy_offset_ready - Clear PHY TX_/RX_OFFSET_READY registers + * @hw: pointer to the HW struct + * + * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted + * and received timestamps as invalid. + */ +int ice_ptp_clear_phy_offset_ready(struct ice_hw *hw) +{ + switch (hw->phy_cfg) { + case ICE_PHY_ETH56G: + return ice_ptp_clear_phy_offset_ready_eth56g(hw); + case ICE_PHY_E830: + case ICE_PHY_E810: + return 0; + case ICE_PHY_E822: + return ice_ptp_clear_phy_offset_ready_e822(hw); + default: + return ICE_ERR_NOT_SUPPORTED; + } +} + /** * ice_read_phy_tstamp - Read a PHY timestamp from the timestamp block * @hw: pointer to the HW struct diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index b1a53e7252..e73aca7503 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -137,6 +137,7 @@ int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval); int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq); int ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj); +int ice_ptp_clear_phy_offset_ready(struct ice_hw *hw); int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp); int -- 2.43.0