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To: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>, dev@dpdk.org
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 <994cdb427701204461ea4f146f8dd240441648e7.1473230641.git.nelio.laranjeiro@6wind.com>
Cc: Vasily Philipov <vasilyf@mellanox.com>
From: Ferruh Yigit <ferruh.yigit@intel.com>
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Date: Wed, 14 Sep 2016 11:43:35 +0100
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Subject: Re: [dpdk-dev] [PATCH 8/8] net/mlx5: fix inline logic
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Hi Nelio,

On 9/7/2016 8:02 AM, Nelio Laranjeiro wrote:
> To improve performance the NIC expects for large packets to have a pointer
> to a cache aligned address, old inline code could break this assumption
> which hurts performance.
> 
> Fixes: 2a66cf378954 ("net/mlx5: support inline send")
> 
> Signed-off-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
> Signed-off-by: Vasily Philipov <vasilyf@mellanox.com>
> ---

...

> @@ -607,8 +523,13 @@ mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
>  				MLX5_ETH_WQE_L3_CSUM |
>  				MLX5_ETH_WQE_L4_CSUM;
>  		} else {
> -			wqe->wqe.eseg.cs_flags = 0;
> +			wqe->eseg.cs_flags = 0;

This cause a compilation error, and looks like a typo:

.../drivers/net/mlx5/mlx5_rxtx.c: In function ‘mlx5_tx_burst’:
.../drivers/net/mlx5/mlx5_rxtx.c:526:7: error: ‘volatile union mlx5_wqe’
has no member named ‘eseg’
    wqe->eseg.cs_flags = 0;
       ^~