From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 736A34404F; Wed, 12 Jun 2024 17:21:19 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B429042F1F; Wed, 12 Jun 2024 17:06:25 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mails.dpdk.org (Postfix) with ESMTP id 024E142FC7 for ; Wed, 12 Jun 2024 17:06:21 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718204782; x=1749740782; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qF2NBRSp9PFzenEiOcNg3ECuNZIySxYg8pIe/7KXcDw=; b=hLeEkKF9BpH7QdKfn+Y2d41kwqbfJtiykoUxoDwsVk94pUzdhpBFT+3C IcehdVxtiJBklOTCGw+kJH0EjbpRnAFvC7bHAnPZCSSuJFuPdViL4cAxB ZUV++tyaxOggm0RGbpw+LOYc6I+F0jk7hybMH4BGQXcGVdYIpfhez/Ubp R5LgBLpAGH2q76deU+jrVIDrWomj2hMUUioNQwEAWyhJ/KupEw3ISsoNp aR2ScTLlFjkYybitVPBtR1zUZjOk3rBdNN3JjRwGustM+p34+IUKCbltr pF6I9KUqyCcegGzT5loHqdSVWieKkRIV4W9eah9ycwrGUePTpsHjjH6c3 w==; X-CSE-ConnectionGUID: 60p67h9bSmiY7RykVgToRw== X-CSE-MsgGUID: 0X6FaeemTRWzJIk+WFffMw== X-IronPort-AV: E=McAfee;i="6700,10204,11101"; a="32459945" X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="32459945" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2024 08:06:22 -0700 X-CSE-ConnectionGUID: py3ynxRZRRGbikIWo6ofPA== X-CSE-MsgGUID: Artt5wozSnuGOmo+fMGP6Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="39925874" Received: from silpixa00401119.ir.intel.com ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 12 Jun 2024 08:06:21 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: ian.stokes@intel.com, bruce.richardson@intel.com Subject: [PATCH v2 112/148] net/ice/base: move ice_ptp_init_phy_model to align with upstream Date: Wed, 12 Jun 2024 16:01:46 +0100 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: <20240430154014.1026-1-ian.stokes@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Upstream code has this function in a different place, so move it to match the upstream code. Signed-off-by: Anatoly Burakov --- drivers/net/ice/base/ice_ptp_hw.c | 127 +++++++++++++++--------------- drivers/net/ice/base/ice_type.h | 6 ++ 2 files changed, 69 insertions(+), 64 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 7413fc891f..f287834a4d 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -2321,70 +2321,6 @@ ice_get_phy_tx_tstamp_ready_eth56g(struct ice_hw *hw, u8 port, return 0; } -#define ICE_DEVID_MASK 0xFFF8 - -/** - * ice_ptp_init_phy_model - Initialize hw->phy_model based on device type - * @hw: pointer to the HW structure - * - * Determine the PHY model for the device, and initialize hw->phy_model - * for use by other functions. - */ -void ice_ptp_init_phy_model(struct ice_hw *hw) -{ - unsigned int phy; - - for (phy = 0; phy < MAX_PHYS_PER_ICE; phy++) - hw->phy_addr[phy] = 0; - - switch (hw->device_id & ICE_DEVID_MASK) { - case ICE_DEV_ID_E825C_BACKPLANE & ICE_DEVID_MASK: - hw->phy_addr[0] = eth56g_dev_0; - hw->phy_addr[1] = eth56g_dev_1; - hw->num_phys = ICE_PHYS_PER_CPLX_C825X; - hw->phy_ports = ICE_PORTS_PER_PHY_C825X; - hw->max_phy_port = ice_is_nac_dual(hw) ? - ICE_PORTS_PER_PHY_C825X : - ICE_PHYS_PER_CPLX_C825X * ICE_PORTS_PER_PHY_C825X; - break; - default: - goto e8xx; - } - - ice_sb_access_ena_eth56g(hw, true); - for (phy = 0; phy < hw->num_phys; phy++) - if (hw->phy_addr[phy]) { - int err; - u32 phy_rev; - - err = ice_read_phy_eth56g_raw_lp(hw, phy, - PHY_REG_REVISION, - &phy_rev, true); - if (err) { - hw->phy_model = ICE_PHY_UNSUP; - return; - } - - if (phy_rev != PHY_REVISION_ETH56G) { - hw->phy_model = ICE_PHY_UNSUP; - return; - } - } - - hw->phy_model = ICE_PHY_ETH56G; - - return; -e8xx: - - if (ice_is_e810(hw)) - hw->phy_model = ICE_PHY_E810; - else - hw->phy_model = ICE_PHY_E822; - - hw->phy_ports = ICE_NUM_EXTERNAL_PORTS; - hw->max_phy_port = ICE_NUM_EXTERNAL_PORTS; -} - /* E822 family functions * * The following functions operate on the E822 family of devices. @@ -5643,6 +5579,69 @@ void ice_ptp_unlock(struct ice_hw *hw) wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0); } +#define ICE_DEVID_MASK 0xFFF8 + +/** + * ice_ptp_init_phy_model - Initialize hw->phy_model based on device type + * @hw: pointer to the HW structure + * + * Determine the PHY model for the device, and initialize hw->phy_model + * for use by other functions. + */ +void ice_ptp_init_phy_model(struct ice_hw *hw) +{ + unsigned int phy; + + for (phy = 0; phy < MAX_PHYS_PER_ICE; phy++) + hw->phy_addr[phy] = 0; + + switch (hw->device_id & ICE_DEVID_MASK) { + case ICE_DEV_ID_E825C_BACKPLANE & ICE_DEVID_MASK: + hw->phy_addr[0] = eth56g_dev_0; + hw->phy_addr[1] = eth56g_dev_1; + hw->num_phys = ICE_PHYS_PER_CPLX_C825X; + hw->phy_ports = ICE_PORTS_PER_PHY_C825X; + hw->max_phy_port = ice_is_nac_dual(hw) ? + ICE_PORTS_PER_PHY_C825X : + ICE_PHYS_PER_CPLX_C825X * ICE_PORTS_PER_PHY_C825X; + break; + default: + goto e8xx; + } + + ice_sb_access_ena_eth56g(hw, true); + for (phy = 0; phy < hw->num_phys; phy++) + if (hw->phy_addr[phy]) { + int err; + u32 phy_rev; + + err = ice_read_phy_eth56g_raw_lp(hw, phy, + PHY_REG_REVISION, + &phy_rev, true); + if (err) { + hw->phy_model = ICE_PHY_UNSUP; + return; + } + + if (phy_rev != PHY_REVISION_ETH56G) { + hw->phy_model = ICE_PHY_UNSUP; + return; + } + } + + hw->phy_model = ICE_PHY_ETH56G; + + return; +e8xx: + + if (ice_is_e810(hw)) + hw->phy_model = ICE_PHY_E810; + else + hw->phy_model = ICE_PHY_E822; + hw->phy_ports = ICE_NUM_EXTERNAL_PORTS; + hw->max_phy_port = ICE_NUM_EXTERNAL_PORTS; +} + /** * ice_ptp_write_port_cmd - Prepare a single PHY port for a timer command * @hw: pointer to HW struct diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index c74da348a3..2754a5a7ca 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -1696,4 +1696,10 @@ struct ice_aq_get_set_rss_lut_params { /* AQ API version for FW auto drop reports */ #define ICE_FW_API_AUTO_DROP_MAJ 1 #define ICE_FW_API_AUTO_DROP_MIN 4 + +static inline bool +ice_is_nac_dual(struct ice_hw *hw) +{ + return !!(hw->dev_caps.nac_topo.mode & ICE_NAC_TOPO_DUAL_M); +} #endif /* _ICE_TYPE_H_ */ -- 2.43.0