From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CE0AFA00C5; Thu, 15 Sep 2022 12:12:08 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5C1DD4021D; Thu, 15 Sep 2022 12:12:08 +0200 (CEST) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mails.dpdk.org (Postfix) with ESMTP id 7337240156 for ; Thu, 15 Sep 2022 12:12:07 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1663236726; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=S0UQeqdV6AnHKo8i55qpvqI2EAekV3lzf80n6ZINQQ4=; b=A1Ws5r+gqht4YEctuhx8cbRwRCZRGfHTxD5F6LF3LOm/mBTT8PQliN6gVFRaK9GPimu+oW R+QGEiyI7CWBfCohKCcYY6f7TMX99dmrzrRnpW3b7KHbWXw+HSgHpfyV0cV3NoXtbUBKeC iukss15J90OlEPhdAMwxBYTyH91EimA= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-312-hpwuWVqIPjm6_Xw5redywg-1; Thu, 15 Sep 2022 06:12:03 -0400 X-MC-Unique: hpwuWVqIPjm6_Xw5redywg-1 Received: from smtp.corp.redhat.com (int-mx09.intmail.prod.int.rdu2.redhat.com [10.11.54.9]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 9006980206D; Thu, 15 Sep 2022 10:12:03 +0000 (UTC) Received: from [10.39.208.12] (unknown [10.39.208.12]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 5C13A49BB60; Thu, 15 Sep 2022 10:12:02 +0000 (UTC) Message-ID: Date: Thu, 15 Sep 2022 12:12:00 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.12.0 Subject: Re: [PATCH v2 22/37] baseband/acc100: enforce additional check on FCW To: Hernan Vargas , dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com References: <20220820023157.189047-1-hernan.vargas@intel.com> <20220820023157.189047-23-hernan.vargas@intel.com> From: Maxime Coquelin In-Reply-To: <20220820023157.189047-23-hernan.vargas@intel.com> X-Scanned-By: MIMEDefang 3.1 on 10.11.54.9 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On 8/20/22 04:31, Hernan Vargas wrote: > Enforce additional check on Frame Control Word validity and add stronger > alignment for decompression mode. As on previous patches, it is a fix and so should be marked appropriately and moved at the beginning of the series. > Signed-off-by: Hernan Vargas > --- > drivers/baseband/acc100/rte_acc100_pmd.c | 40 ++++++++++++++++++++++-- > 1 file changed, 37 insertions(+), 3 deletions(-) > > diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c > index ea850e2d7f..d67495ac52 100644 > --- a/drivers/baseband/acc100/rte_acc100_pmd.c > +++ b/drivers/baseband/acc100/rte_acc100_pmd.c > @@ -1508,6 +1508,20 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, > fcw->hcin_offset = 0; > fcw->hcin_size1 = 0; > } > + /* Enforce additional check on FCW validity */ > + uint32_t max_hc_in = RTE_ALIGN_CEIL(fcw->ncb - fcw->nfiller, 64); Don't mix declaration and code. > + if ((fcw->hcin_size0 > max_hc_in) || > + (fcw->hcin_size1 + fcw->hcin_offset > max_hc_in) || > + ((fcw->hcin_size0 > fcw->hcin_offset) && > + (fcw->hcin_size1 != 0))) { > + rte_bbdev_log(ERR, " Invalid FCW : HCIn %d %d %d, Ncb %d F %d", > + fcw->hcin_size0, fcw->hcin_size1, > + fcw->hcin_offset, > + fcw->ncb, fcw->nfiller); > + /* Disable HARQ input in that case to carry forward */ > + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; > + fcw->hcin_en = 0; > + } > > fcw->itmax = op->ldpc_dec.iter_max; > fcw->itstop = check_bit(op->ldpc_dec.op_flags, > @@ -1536,10 +1550,19 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, > k0_p = (fcw->k0 > parity_offset) ? > fcw->k0 - op->ldpc_dec.n_filler : fcw->k0; > ncb_p = fcw->ncb - op->ldpc_dec.n_filler; > - l = k0_p + fcw->rm_e; > + l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX); > harq_out_length = (uint16_t) fcw->hcin_size0; > - harq_out_length = RTE_MIN(RTE_MAX(harq_out_length, l), ncb_p); > - harq_out_length = (harq_out_length + 0x3F) & 0xFFC0; > + harq_out_length = RTE_MAX(harq_out_length, l); > + /* Stronger alignment when in compression mode */ > + if (fcw->hcout_comp_mode > 0) > + harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 256); A define would make sense instead of raw value > + /* Cannot exceed the pruned Ncb circular buffer */ > + harq_out_length = RTE_MIN(harq_out_length, ncb_p); > + /* Alignment on next 64B */ > + harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 64); > + /* Stronger alignment when in compression mode enforced again */ > + if (fcw->hcout_comp_mode > 0) > + harq_out_length = RTE_ALIGN_FLOOR(harq_out_length, 256); > if ((k0_p > fcw->hcin_size0 + ACC100_HARQ_OFFSET_THRESHOLD) && > harq_prun) { > fcw->hcout_size0 = (uint16_t) fcw->hcin_size0; > @@ -1550,6 +1573,13 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, > fcw->hcout_size1 = 0; > fcw->hcout_offset = 0; > } > + if (fcw->hcout_size0 == 0) { > + rte_bbdev_log(ERR, " Invalid FCW : HCout %d", > + fcw->hcout_size0); > + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE; > + fcw->hcout_en = 0; > + } > + > harq_layout[harq_index].offset = fcw->hcout_offset; > harq_layout[harq_index].size0 = fcw->hcout_size0; > } else { > @@ -1591,6 +1621,10 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, > /* Disable HARQ input in that case to carry forward */ > op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; > } > + if (unlikely(fcw->rm_e == 0)) { > + rte_bbdev_log(WARNING, "Null E input provided"); > + fcw->rm_e = 2; > + } > > fcw->hcin_en = check_bit(op->ldpc_dec.op_flags, > RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE);