From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id A4A50A09D9; Wed, 11 Nov 2020 17:13:16 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 6E88BF64; Wed, 11 Nov 2020 17:13:15 +0100 (CET) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id 9878A23D for ; Wed, 11 Nov 2020 17:13:13 +0100 (CET) IronPort-SDR: QWERjb7avrYBF+CYHBcMlJOGSoxS1I/tqMh+OZIbgU4jQ9hIF1da99hOVv4Rvmc/weM52d+HMa uGVkHnBG8zMA== X-IronPort-AV: E=McAfee;i="6000,8403,9802"; a="150019438" X-IronPort-AV: E=Sophos;i="5.77,469,1596524400"; d="scan'208";a="150019438" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Nov 2020 08:13:09 -0800 IronPort-SDR: J0+xwG+Zu5eI5oeKvdzsarPkSgu+iyT0WocRRQp0tJQQSKXN12fTxxe7QRG2M5tFqxMSMH2Glo +7JEhvkK5XAg== X-IronPort-AV: E=Sophos;i="5.77,469,1596524400"; d="scan'208";a="473905641" Received: from fyigit-mobl1.ger.corp.intel.com (HELO [10.213.241.123]) ([10.213.241.123]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Nov 2020 08:13:08 -0800 To: Jiawen Wu , dev@dpdk.org References: <20201111064936.768604-1-jiawenwu@trustnetic.com> <20201111064936.768604-33-jiawenwu@trustnetic.com> From: Ferruh Yigit Message-ID: Date: Wed, 11 Nov 2020 16:13:06 +0000 MIME-Version: 1.0 In-Reply-To: <20201111064936.768604-33-jiawenwu@trustnetic.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH v2 32/37] net/txgbe: add macsec setting X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 11/11/2020 6:49 AM, Jiawen Wu wrote: > Add macsec register enable and setting reset operations. > Add macsec offload suuport. > > Signed-off-by: Jiawen Wu <...> > @@ -1763,6 +1767,10 @@ txgbe_dev_start(struct rte_eth_dev *dev) > */ > txgbe_dev_link_update(dev, 0); > > + /* setup the macsec ctrl register */ > + if (macsec_setting->offload_en) > + txgbe_dev_macsec_register_enable(dev, macsec_setting); > + Is there any piece of code that sets 'offload_en'? This looks like all new added code is dead code and not called at all... <...> > +++ b/drivers/net/txgbe/txgbe_rxtx.c > @@ -56,6 +56,9 @@ static const u64 TXGBE_TX_OFFLOAD_MASK = (PKT_TX_IP_CKSUM | > PKT_TX_L4_MASK | > PKT_TX_TCP_SEG | > PKT_TX_TUNNEL_MASK | > +#ifdef RTE_LIBRTE_MACSEC > + PKT_TX_MACSEC | > +#endif Where this macro defined? Who enables it?