From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E1A2FA034F; Mon, 30 Aug 2021 13:11:14 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C697841171; Mon, 30 Aug 2021 13:11:14 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 1C3E241170 for ; Mon, 30 Aug 2021 13:11:12 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 17U2EDHn025256 for ; Mon, 30 Aug 2021 04:11:12 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=AXORyE7ICKGgDeYk8jUgq3d+l44nAIKHJ6dKCS+CLcQ=; b=HKErQ6bVaolsIVZIxM5S2Bx+EZzm5aVvUS0llJZ9BRWc8/mn6tBt47+LVMZGSD0nN7W9 I6z3WIyVAtTePKk4AHzF3TUQwjKeAUhkJkETez1mj7ddxw+gk7TeFCY9LucxY1v70x9z BUKYWVhZzyEsf4Cdhnkx8o4xLK2bYtcd9Oqj6uTWVjPhAKyiY5zSk1btZ1uyg6y2bHUd mayecjFJVnAEG95VKxFE6ZBzfmSjMGDuMixjo5CE594RI7E7hX6aQwlzMF9uW20I7tgz WOzTLWGVslwqKmL7zEIP9sy/WyomfxIwQTYQoioNN7swmR4oh5iTpSUREIA1KpWOij9O kg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 3arpcahg5n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 30 Aug 2021 04:11:12 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 30 Aug 2021 04:11:10 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 30 Aug 2021 04:11:10 -0700 Received: from localhost.localdomain (unknown [10.28.34.29]) by maili.marvell.com (Postfix) with ESMTP id EA27F3F707D; Mon, 30 Aug 2021 04:11:07 -0700 (PDT) From: Shijith Thotton To: CC: Shijith Thotton , , , , , , Kiran Kumar K , "Sunil Kumar Kori" , Satha Rao Date: Mon, 30 Aug 2021 16:39:10 +0530 Message-ID: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: Es6BgG--HthDsQ27L-fW8P8NNp_jOrqR X-Proofpoint-ORIG-GUID: Es6BgG--HthDsQ27L-fW8P8NNp_jOrqR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-08-30_04,2021-08-30_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH 1/8] net/cnxk: add flag to show CPT can enqueue events X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" CPT can be told to submit events to SSO upon completion. Crypto adapter uses this feature and the new flag can be used to optimize receive path in those cases. Signed-off-by: Shijith Thotton --- drivers/net/cnxk/cn10k_rx.h | 5 +++-- drivers/net/cnxk/cn9k_rx.h | 3 ++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h index 4c5288b2cc..68219b8c19 100644 --- a/drivers/net/cnxk/cn10k_rx.h +++ b/drivers/net/cnxk/cn10k_rx.h @@ -21,8 +21,9 @@ * Defining it from backwards to denote its been * not used as offload flags to pick function */ -#define NIX_RX_VWQE_F BIT(14) -#define NIX_RX_MULTI_SEG_F BIT(15) +#define NIX_RX_VWQE_F BIT(13) +#define NIX_RX_MULTI_SEG_F BIT(14) +#define CPT_RX_WQE_F BIT(15) #define CNXK_NIX_CQ_ENTRY_SZ 128 #define NIX_DESCS_PER_LOOP 4 diff --git a/drivers/net/cnxk/cn9k_rx.h b/drivers/net/cnxk/cn9k_rx.h index beb52f39d5..a3bf4e0b63 100644 --- a/drivers/net/cnxk/cn9k_rx.h +++ b/drivers/net/cnxk/cn9k_rx.h @@ -22,7 +22,8 @@ * Defining it from backwards to denote its been * not used as offload flags to pick function */ -#define NIX_RX_MULTI_SEG_F BIT(15) +#define NIX_RX_MULTI_SEG_F BIT(14) +#define CPT_RX_WQE_F BIT(15) #define CNXK_NIX_CQ_ENTRY_SZ 128 #define NIX_DESCS_PER_LOOP 4 -- 2.25.1