From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B7BC5A054F; Tue, 2 Mar 2021 14:01:44 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 46CC322A328; Tue, 2 Mar 2021 14:01:44 +0100 (CET) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id E3BCC40142 for ; Tue, 2 Mar 2021 14:01:42 +0100 (CET) IronPort-SDR: JUyh+UvK5FsmynrQDrYGg4LmuEqwdl7tZrRA++sfPuCUWdrA+YVkA8EB3/2c51X32XOnO0pJsM mFFqZtb5kiHQ== X-IronPort-AV: E=McAfee;i="6000,8403,9910"; a="271807541" X-IronPort-AV: E=Sophos;i="5.81,216,1610438400"; d="scan'208";a="271807541" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2021 05:01:34 -0800 IronPort-SDR: oBc/m2OxeRwVkUFX3vcQMoB9AM3ovMoR5EjlDGUKg6kvCeZresetBSXJrneBmBqyRgnhjrhuL+ bYl1bLxh7iuA== X-IronPort-AV: E=Sophos;i="5.81,216,1610438400"; d="scan'208";a="406697079" Received: from fyigit-mobl1.ger.corp.intel.com (HELO [10.213.252.162]) ([10.213.252.162]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2021 05:01:32 -0800 To: =?UTF-8?B?6LCi5Y2O5LyfKOatpOaXtuatpOWIu++8iQ==?= , maxime.coquelin@redhat.com, david.marchand@redhat.com Cc: dev@dpdk.org, anatoly.burakov@intel.com, xuemingl@nvidia.com, grive@u256.net, chenbo.xia@intel.com References: <1614014118-91150-1-git-send-email-huawei.xhw@alibaba-inc.com> <1614614483-75891-1-git-send-email-huawei.xhw@alibaba-inc.com> <50960672-267a-a8b7-2474-3534314b3db7@alibaba-inc.com> From: Ferruh Yigit X-User: ferruhy Message-ID: Date: Tue, 2 Mar 2021 13:01:28 +0000 MIME-Version: 1.0 In-Reply-To: <50960672-267a-a8b7-2474-3534314b3db7@alibaba-inc.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH v8 0/2] support both PIO and MMIO BAR for legacy device in virtio PMD X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 3/2/2021 12:48 PM, 谢华伟(此时此刻） wrote: Please don't top post, message moved down. > On 2021/3/2 0:01, 谢华伟(此时此刻） wrote: >> From: "huawei.xhw" >> >> virtio PMD assumes legacy device only supports PIO BAR resource. This is wrong. >> As we need to create lots of devices, as PIO resource on x86 is very limited, >> we expose MMIO(memory IO) BAR. >> >> Kernel supports both PIO and MMIO BAR for legacy virtio-pci device, and for all >> other pci devices. This patchset handles different type of BAR in the similar >> way. >> >> In previous implementation, under igb_uio driver we get PIO address from igb_uio >> sysfs entry; with uio_pci_generic, we get PIO address from /proc/ioports for x86, >> and for other ARCHs, we get PIO address from standard PCI sysfs entry. >> For PIO/MMIO RW, there is different path for different drivers and arch. > > Hi David and ferru: > > Any other issue integrating this patch? > As far as I can see the 'outw_p' to 'outw' conversion is not clarified. Before this patch, 'outw_p' was used, now 'outw' is used, right? And this seem to optimize the performance, so the suggestion was to separate this change into another patch, what do you think about this?