From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E0DD3A0C4F; Fri, 16 Jul 2021 11:43:17 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9E0EB41361; Fri, 16 Jul 2021 11:43:16 +0200 (CEST) Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by mails.dpdk.org (Postfix) with ESMTP id 3724D4135D; Fri, 16 Jul 2021 11:43:14 +0200 (CEST) Received: from dggemv703-chm.china.huawei.com (unknown [172.30.72.54]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4GR5n53jqHzcf5W; Fri, 16 Jul 2021 17:39:53 +0800 (CST) Received: from dggpeml500019.china.huawei.com (7.185.36.137) by dggemv703-chm.china.huawei.com (10.3.19.46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Fri, 16 Jul 2021 17:43:12 +0800 Received: from tester.localdomain (10.175.119.39) by dggpeml500019.china.huawei.com (7.185.36.137) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Fri, 16 Jul 2021 17:43:11 +0800 From: Guoyang Zhou To: CC: , , , , , , , , , , , Date: Fri, 16 Jul 2021 17:54:30 +0800 Message-ID: X-Mailer: git-send-email 1.8.3.1 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.175.119.39] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To dggpeml500019.china.huawei.com (7.185.36.137) X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH v1 3/3] net/hinic: fix the problem of MTU inconsistent X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The configuration of mtu is inconsistent in the driver and firmware when the port is stopped, started and reconfigured. Before, HINIC_MAX_JUMBO_FRAME_SIZE include vlan tag, but when frame and pktlen are converted to each other do not include vlan tag. And port_mtu_set function will use HINIC_MAX_JUMBO_FRAME_SIZE to calculate eth_overhead, so mtu will be inconsistent in the driver and firmware. Fixes: e542ab51ab27 ("net/hinic: fix jumbo frame flag condition for MTU set") Cc: stable@dpdk.org Signed-off-by: Guoyang Zhou --- drivers/net/hinic/base/hinic_pmd_niccfg.h | 9 --------- drivers/net/hinic/hinic_pmd_ethdev.c | 9 --------- drivers/net/hinic/hinic_pmd_ethdev.h | 17 +++++++++++++++++ 3 files changed, 17 insertions(+), 18 deletions(-) diff --git a/drivers/net/hinic/base/hinic_pmd_niccfg.h b/drivers/net/hinic/base/hinic_pmd_niccfg.h index 04cd374..0d0a670 100644 --- a/drivers/net/hinic/base/hinic_pmd_niccfg.h +++ b/drivers/net/hinic/base/hinic_pmd_niccfg.h @@ -116,15 +116,6 @@ enum hinic_link_mode { #define HINIC_DEFAULT_RX_MODE (HINIC_RX_MODE_UC | HINIC_RX_MODE_MC | \ HINIC_RX_MODE_BC) -#define HINIC_MAX_MTU_SIZE (9600) -#define HINIC_MIN_MTU_SIZE (256) - -/* MIN_MTU + ETH_HLEN + CRC (256+14+4) */ -#define HINIC_MIN_FRAME_SIZE 274 - -/* MAX_MTU + ETH_HLEN + CRC + VLAN(9600+14+4+4) */ -#define HINIC_MAX_JUMBO_FRAME_SIZE (9622) - #define HINIC_PORT_DISABLE 0x0 #define HINIC_PORT_ENABLE 0x3 diff --git a/drivers/net/hinic/hinic_pmd_ethdev.c b/drivers/net/hinic/hinic_pmd_ethdev.c index 75849f2..1a72401 100644 --- a/drivers/net/hinic/hinic_pmd_ethdev.c +++ b/drivers/net/hinic/hinic_pmd_ethdev.c @@ -69,15 +69,6 @@ #define HINIC_VLAN_FILTER_EN (1U << 0) -#define HINIC_MTU_TO_PKTLEN(mtu) \ - ((mtu) + ETH_HLEN + ETH_CRC_LEN) - -#define HINIC_PKTLEN_TO_MTU(pktlen) \ - ((pktlen) - (ETH_HLEN + ETH_CRC_LEN)) - -/* The max frame size with default MTU */ -#define HINIC_ETH_MAX_LEN (RTE_ETHER_MTU + ETH_HLEN + ETH_CRC_LEN) - /* lro numer limit for one packet */ #define HINIC_LRO_WQE_NUM_DEFAULT 8 diff --git a/drivers/net/hinic/hinic_pmd_ethdev.h b/drivers/net/hinic/hinic_pmd_ethdev.h index 70b4d32..8f1b3d5 100644 --- a/drivers/net/hinic/hinic_pmd_ethdev.h +++ b/drivers/net/hinic/hinic_pmd_ethdev.h @@ -32,6 +32,23 @@ #define HINIC_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t)) #define HINIC_VFTA_SIZE (4096 / HINIC_UINT32_BIT_SIZE) +#define HINIC_MAX_MTU_SIZE 9600 +#define HINIC_MIN_MTU_SIZE 256 + +#define HINIC_VLAN_TAG_SIZE 4 +#define HINIC_ETH_OVERHEAD \ + (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HINIC_VLAN_TAG_SIZE * 2) + +#define HINIC_MIN_FRAME_SIZE (HINIC_MIN_MTU_SIZE + HINIC_ETH_OVERHEAD) +#define HINIC_MAX_JUMBO_FRAME_SIZE (HINIC_MAX_MTU_SIZE + HINIC_ETH_OVERHEAD) + +#define HINIC_MTU_TO_PKTLEN(mtu) ((mtu) + HINIC_ETH_OVERHEAD) + +#define HINIC_PKTLEN_TO_MTU(pktlen) ((pktlen) - HINIC_ETH_OVERHEAD) + +/* The max frame size with default MTU */ +#define HINIC_ETH_MAX_LEN (RTE_ETHER_MTU + HINIC_ETH_OVERHEAD) + enum hinic_dev_status { HINIC_DEV_INIT, HINIC_DEV_CLOSE, -- 1.8.3.1