From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BEF14A0C4C; Thu, 2 Sep 2021 16:43:06 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A6D6A4003E; Thu, 2 Sep 2021 16:43:06 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 461894003C for ; Thu, 2 Sep 2021 16:43:05 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18281Et4011520 for ; Thu, 2 Sep 2021 07:43:04 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=AXORyE7ICKGgDeYk8jUgq3d+l44nAIKHJ6dKCS+CLcQ=; b=hsJCugV/twhJ148QxExEncQLiJIjCeZavJazEIZ0Yi8gy+Iyr02b/GKu9/6foXJJAWMs vurt7c6w5Lk3KQ/UNs7Ch+C569lw3S5TDmsVPt+Qi9lnXnOg2XW7pnrVprjmEpD626oL QnldAYnPTmKEDvlBtx6FqBDmp3XoopVDzXtNgMr1XuZNcyb9+Ubvz9SJt//ykrdWXpOX XVyEUmHlVI9VdnlQJt5+atnszknk6gyjuh0RrQfzQ0VpiR+wCv9+9iF1/jooiTx+QbrK AgUQoePmqxAynAT/IeHY81DWhizpCgFt3rd79XH55uEqO8EzAz8V6C/lCCMRWGWUWr9/ 3w== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 3attqmhc6p-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 02 Sep 2021 07:43:04 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 2 Sep 2021 07:43:03 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 2 Sep 2021 07:43:03 -0700 Received: from localhost.localdomain (unknown [10.28.34.29]) by maili.marvell.com (Postfix) with ESMTP id 628283F705E; Thu, 2 Sep 2021 07:43:00 -0700 (PDT) From: Shijith Thotton To: CC: Shijith Thotton , , , , , , Kiran Kumar K , "Sunil Kumar Kori" , Satha Rao Date: Thu, 2 Sep 2021 20:11:49 +0530 Message-ID: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: HzMcB_enr2Szje0DSJ5sWgPuFc3UzI58 X-Proofpoint-ORIG-GUID: HzMcB_enr2Szje0DSJ5sWgPuFc3UzI58 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-02_04,2021-09-02_03,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 1/8] net/cnxk: add flag to show CPT can enqueue events X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" CPT can be told to submit events to SSO upon completion. Crypto adapter uses this feature and the new flag can be used to optimize receive path in those cases. Signed-off-by: Shijith Thotton --- drivers/net/cnxk/cn10k_rx.h | 5 +++-- drivers/net/cnxk/cn9k_rx.h | 3 ++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h index 4c5288b2cc..68219b8c19 100644 --- a/drivers/net/cnxk/cn10k_rx.h +++ b/drivers/net/cnxk/cn10k_rx.h @@ -21,8 +21,9 @@ * Defining it from backwards to denote its been * not used as offload flags to pick function */ -#define NIX_RX_VWQE_F BIT(14) -#define NIX_RX_MULTI_SEG_F BIT(15) +#define NIX_RX_VWQE_F BIT(13) +#define NIX_RX_MULTI_SEG_F BIT(14) +#define CPT_RX_WQE_F BIT(15) #define CNXK_NIX_CQ_ENTRY_SZ 128 #define NIX_DESCS_PER_LOOP 4 diff --git a/drivers/net/cnxk/cn9k_rx.h b/drivers/net/cnxk/cn9k_rx.h index beb52f39d5..a3bf4e0b63 100644 --- a/drivers/net/cnxk/cn9k_rx.h +++ b/drivers/net/cnxk/cn9k_rx.h @@ -22,7 +22,8 @@ * Defining it from backwards to denote its been * not used as offload flags to pick function */ -#define NIX_RX_MULTI_SEG_F BIT(15) +#define NIX_RX_MULTI_SEG_F BIT(14) +#define CPT_RX_WQE_F BIT(15) #define CNXK_NIX_CQ_ENTRY_SZ 128 #define NIX_DESCS_PER_LOOP 4 -- 2.25.1