From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 444DAA04C4; Thu, 14 Nov 2019 00:08:26 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BC8042B8B; Thu, 14 Nov 2019 00:08:24 +0100 (CET) Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by dpdk.org (Postfix) with ESMTP id 394C923D for ; Thu, 14 Nov 2019 00:08:23 +0100 (CET) Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id xADN3ETa047158; Wed, 13 Nov 2019 18:08:19 -0500 Received: from ppma04dal.us.ibm.com (7a.29.35a9.ip4.static.sl-reverse.com [169.53.41.122]) by mx0a-001b2d01.pphosted.com with ESMTP id 2w8rw0mp49-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 13 Nov 2019 18:08:19 -0500 Received: from pps.filterd (ppma04dal.us.ibm.com [127.0.0.1]) by ppma04dal.us.ibm.com (8.16.0.27/8.16.0.27) with SMTP id xADN5H42023325; Wed, 13 Nov 2019 23:08:18 GMT Received: from b03cxnp07028.gho.boulder.ibm.com (b03cxnp07028.gho.boulder.ibm.com [9.17.130.15]) by ppma04dal.us.ibm.com with ESMTP id 2w5n36y2au-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 13 Nov 2019 23:08:18 +0000 Received: from b03ledav003.gho.boulder.ibm.com (b03ledav003.gho.boulder.ibm.com [9.17.130.234]) by b03cxnp07028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xADN8HfD7340344 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 13 Nov 2019 23:08:17 GMT Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7BAC46A079; Wed, 13 Nov 2019 23:08:17 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BF8FC6A05D; Wed, 13 Nov 2019 23:08:15 +0000 (GMT) Received: from davids-mbp.usor.ibm.com (unknown [9.70.84.79]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 13 Nov 2019 23:08:15 +0000 (GMT) To: Jerin Jacob Kollanukkaran , "dev@dpdk.org" Cc: Olivier Matz , Andrew Rybchenko , "bruce.richardson@intel.com" , "konstantin.ananyev@intel.com" , "hemant.agrawal@nxp.com" , Shahaf Shuler , Honnappa Nagarahalli , Gavin Hu , "viktorin@rehivetech.com" , "anatoly.burakov@intel.com" References: From: David Christensen Message-ID: Date: Wed, 13 Nov 2019 15:08:15 -0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-11-13_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=843 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1910280000 definitions=main-1911130192 Subject: Re: [dpdk-dev] Mbuf memory alignment constraints for (micro)architectures X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > # Is PPC and other ARM SoC has formula (B) to compute DRAM channel distribution ? or > Is it specific to x86? That would define where the hooks needs to added to have proper fix. The Power 9 chip has eight memory channels, each with a dedicated memory controller unit (MCU). The MCUs can be configured into one or more address interleave groups (with 1, 2, 3, 4, 6, or 8 MCUs), with a programmable interleave granularity of 128B to 32KB. Trying to find more info on how to access this configuration data and expose it to the DPDK. Dave