From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E9F2542963; Sat, 22 Apr 2023 02:30:02 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BFAFA40EF1; Sat, 22 Apr 2023 02:30:02 +0200 (CEST) Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by mails.dpdk.org (Postfix) with ESMTP id E07DB40ED5 for ; Sat, 22 Apr 2023 02:30:00 +0200 (CEST) Received: from loongson.cn (unknown [223.72.41.205]) by gateway (Coremail) with SMTP id _____8DxJYyGKkNkeEQgAA--.50180S3; Sat, 22 Apr 2023 08:29:59 +0800 (CST) Received: from [192.168.1.14] (unknown [223.72.41.205]) by localhost.localdomain (Coremail) with SMTP id AQAAf8DxwOSFKkNkaQ00AA--.34041S3; Sat, 22 Apr 2023 08:29:58 +0800 (CST) Message-ID: Date: Sat, 22 Apr 2023 08:29:58 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH 1/1] net/ixgbe: add a proper memory barrier for LoongArch To: zhoumin , qiming.yang@intel.com, wenjun1.wu@intel.com Cc: dev@dpdk.org References: <20230407085041.3966259-1-zhoumin@loongson.cn> <1cfdd578-774d-f9e8-da23-4b7c29a370c5@loongson.cn> From: "bibo, mao" In-Reply-To: <1cfdd578-774d-f9e8-da23-4b7c29a370c5@loongson.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-CM-TRANSID: AQAAf8DxwOSFKkNkaQ00AA--.34041S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjvJXoWxJrWUZr4UKFy3ZryfAw13urg_yoW8KrW7pF n5Jr1jkryUGw48Jw1xXw15WryDAr4xXa1UG3sYya4DArWDXryjqr1jqry09ryDJr48J3WI vr4UZw45ZFZxZw7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU bx8YFVCjjxCrM7AC8VAFwI0_Jr0_Gr1l1xkIjI8I6I8E6xAIw20EY4v20xvaj40_Wr0E3s 1l1IIY67AEw4v_Jr0_Jr4l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xv wVC0I7IYx2IY67AKxVWUJVWUCwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwA2z4 x0Y4vEx4A2jsIE14v26r1j6r4UM28EF7xvwVC2z280aVCY1x0267AKxVWUJVW8JwAS0I0E 0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI0UMc02F40EFcxC0VAKzV Aqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S 6xCaFVCjc4AY6r1j6r4UM4x0Y48IcVAKI48JMxk0xIA0c2IEe2xFo4CEbIxvr21l42xK82 IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC2 0s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMI IF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF 0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87 Iv6xkF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x07UE-erUUUUU= X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org 在 2023/4/21 9:12, zhoumin 写道: > On Fri, Apr 7, 2023 at 4:50PM, Min Zhou wrote: >> Segmentation fault has been observed while running the >> ixgbe_recv_pkts_lro() function to receive packets on the Loongson >> 3C5000 processor which has 64 cores and 4 NUMA nodes. >> >> Reason is the read ordering of the status and the rest of the >> descriptor fields in this function may not be correct on the >> LoongArch processor. We should add rte_rmb() to ensure the read >> ordering be correct. >> >> We also did the same thing in the ixgbe_recv_pkts() function. >> >> Signed-off-by: Min Zhou >> --- >>   drivers/net/ixgbe/ixgbe_rxtx.c | 6 ++++++ >>   1 file changed, 6 insertions(+) >> >> diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c >> b/drivers/net/ixgbe/ixgbe_rxtx.c >> index c9d6ca9efe..16391a42f9 100644 >> --- a/drivers/net/ixgbe/ixgbe_rxtx.c >> +++ b/drivers/net/ixgbe/ixgbe_rxtx.c >> @@ -1823,6 +1823,9 @@ ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf >> **rx_pkts, >>           staterr = rxdp->wb.upper.status_error; >>           if (!(staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))) >>               break; >> +#if defined(RTE_ARCH_LOONGARCH) >> +        rte_rmb(); >> +#endif >>           rxd = *rxdp; Hi Min, Could you add more detailed analysis aboout the issu? Althrough rxdp is declared as volatile, which is only in order for compiler. However some architectures like LoongArch are weak-ordered. For this piece of code: 1: staterr = rxdp->wb.upper.status_error; Sentence 1 can be execute after sentence 1, dd indicated that packet is ready with new value. 2: rxd = *rxdp; Sentence 2 can be execute first and get old value. .......Balabala Regards Bibo, Mao >>           /* >> @@ -2122,6 +2125,9 @@ ixgbe_recv_pkts_lro(void *rx_queue, struct >> rte_mbuf **rx_pkts, uint16_t nb_pkts, >>           if (!(staterr & IXGBE_RXDADV_STAT_DD)) >>               break; >> +#if defined(RTE_ARCH_LOONGARCH) >> +        rte_rmb(); >> +#endif >>           rxd = *rxdp; >>           PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u " > > Kindly ping. > > Any comments or suggestions will be appreciated. > > > Min >