* [PATCH 2/2] net/mlx5: update devarg according to SWS support
2025-04-27 11:19 [PATCH 1/2] common/mlx5: read SWS capability bits Maayan Kashani
@ 2025-04-27 11:19 ` Maayan Kashani
2025-05-13 6:23 ` [PATCH 1/2] common/mlx5: read SWS capability bits Raslan Darawsheh
1 sibling, 0 replies; 3+ messages in thread
From: Maayan Kashani @ 2025-04-27 11:19 UTC (permalink / raw)
To: dev
Cc: mkashani, dsosnowski, rasland, Viacheslav Ovsiienko, Bing Zhao,
Ori Kam, Suanming Mou, Matan Azrad
SWS will be disabled in future HW generation.
Update default for dv_flow_en/allow_duplicate_pattern devargs and
return relevant error if user configuration is not supported.
Signed-off-by: Maayan Kashani <mkashani@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
doc/guides/nics/mlx5.rst | 10 +++++++---
drivers/net/mlx5/mlx5.c | 25 +++++++++++++++++++++++--
2 files changed, 30 insertions(+), 5 deletions(-)
diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 08f3648e993..3a8879939f9 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -1546,8 +1546,11 @@ for an additional list of options shared with other mlx5 drivers.
Value 2 enables the WQE based hardware steering.
In this mode, only queue-based flow management is supported.
- It is configured by default to 1 (DV flow steering) if supported.
- Otherwise, the value is 0 which indicates legacy Verbs flow offloading.
+ Default configuration depends on HW capabilities:
+
+ - If DV flow steering is supported, it will be set to 1.
+ - Otherwise, if HW steering is supported, it will be set to 2.
+ - Otherwise, PMD will fallback to legacy Verbs and it will be set to 0.
- ``dv_esw_en`` parameter [int]
@@ -1680,7 +1683,8 @@ for an additional list of options shared with other mlx5 drivers.
In this case, all rules are inserted but only the first rule takes effect,
the next rule takes effect only if the previous rules are deleted.
- By default, the PMD will set this value to 1.
+ By default, the PMD will set this value according to capability
+ (For NICs supporting DV flow steering, it will be set 1. Otherwise, it will be set to 0.).
Multiport E-Switch
diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index 646da8e846c..03f6db5ecd7 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -1488,14 +1488,23 @@ mlx5_shared_dev_ctx_args_config(struct mlx5_dev_ctx_shared *sh,
NULL,
};
int ret = 0;
+ struct mlx5_hca_attr *attr = &sh->cdev->config.hca_attr;
+ bool sws_is_supported = (attr->sw_owner ||
+ (attr->sw_owner_v2 &&
+ attr->steering_format_version <= MLX5_STEERING_LOGIC_FORMAT_CONNECTX_8));
/* Default configuration. */
memset(config, 0, sizeof(*config));
config->vf_nl_en = 1;
config->dv_esw_en = 1;
- config->dv_flow_en = 1;
+ if (sws_is_supported) {
+ config->dv_flow_en = 1;
+ config->allow_duplicate_pattern = 1;
+ } else {
+ config->dv_flow_en = 2;
+ config->allow_duplicate_pattern = 0;
+ }
config->decap_en = 1;
- config->allow_duplicate_pattern = 1;
config->fdb_def_rule = 1;
config->cnt_svc.cycle_time = MLX5_CNT_SVC_CYCLE_TIME_DEFAULT;
config->cnt_svc.service_core = rte_get_main_lcore();
@@ -1510,6 +1519,18 @@ mlx5_shared_dev_ctx_args_config(struct mlx5_dev_ctx_shared *sh,
return -rte_errno;
}
}
+ if (!sws_is_supported) {
+ if (config->dv_flow_en == 1) {
+ DRV_LOG(ERR, "DV flow steering is not supported.");
+ rte_errno = ENODEV;
+ return -rte_errno;
+ }
+ if (config->allow_duplicate_pattern == 1) {
+ DRV_LOG(ERR, "Duplicate pattern is not allowed.");
+ rte_errno = ENODEV;
+ return -rte_errno;
+ }
+ }
/* Adjust parameters according to device capabilities. */
if (config->dv_flow_en && !sh->dev_cap.dv_flow_en) {
DRV_LOG(WARNING, "DV flow is not supported.");
--
2.21.0
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH 1/2] common/mlx5: read SWS capability bits
2025-04-27 11:19 [PATCH 1/2] common/mlx5: read SWS capability bits Maayan Kashani
2025-04-27 11:19 ` [PATCH 2/2] net/mlx5: update devarg according to SWS support Maayan Kashani
@ 2025-05-13 6:23 ` Raslan Darawsheh
1 sibling, 0 replies; 3+ messages in thread
From: Raslan Darawsheh @ 2025-05-13 6:23 UTC (permalink / raw)
To: Maayan Kashani, dev
Cc: dsosnowski, Viacheslav Ovsiienko, Bing Zhao, Ori Kam,
Suanming Mou, Matan Azrad
Hi,
On 27/04/2025 2:19 PM, Maayan Kashani wrote:
> SWS will be disabled in future HW generation.
> Checking SWS capability bits and returning relevant error.
> if user configuration is not supported,
> will be added in the follow up commit.
>
> Signed-off-by: Maayan Kashani <mkashani@nvidia.com>
> Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Series applied to next-net-mlx,
--
Kindest regards
Raslan Darawsheh
^ permalink raw reply [flat|nested] 3+ messages in thread