From mboxrd@z Thu Jan 1 00:00:00 1970
Return-Path: <dev-bounces@dpdk.org>
Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124])
by inbox.dpdk.org (Postfix) with ESMTP id 2B5AEA09FF;
Mon, 11 Jan 2021 15:59:18 +0100 (CET)
Received: from [217.70.189.124] (localhost [127.0.0.1])
by mails.dpdk.org (Postfix) with ESMTP id 4137F140EA1;
Mon, 11 Jan 2021 15:59:06 +0100 (CET)
Received: from mga17.intel.com (mga17.intel.com [192.55.52.151])
by mails.dpdk.org (Postfix) with ESMTP id BFFDB140E92
for <dev@dpdk.org>; Mon, 11 Jan 2021 15:59:03 +0100 (CET)
IronPort-SDR: etv5PWl9oPYuvhLYz+/i0WZb4/LY2UPZAL+My9XEGhstUPIx3SxyO0Z7pJiCnxOE5eQISliq/s
JUJHkf7E0q/Q==
X-IronPort-AV: E=McAfee;i="6000,8403,9860"; a="157652991"
X-IronPort-AV: E=Sophos;i="5.79,338,1602572400"; d="scan'208";a="157652991"
Received: from orsmga001.jf.intel.com ([10.7.209.18])
by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;
11 Jan 2021 06:59:03 -0800
IronPort-SDR: P2FS/RA47mrdoPI537Qb1dbyh1cSuVpWzDhSAr/sSxm9HPQSTzRujxqTNfls7IYVa44uW2VgC+
636qbKqT2Jng==
X-ExtLoop1: 1
X-IronPort-AV: E=Sophos;i="5.79,338,1602572400"; d="scan'208";a="423816537"
Received: from silpixa00399498.ir.intel.com (HELO
silpixa00399498.ger.corp.intel.com) ([10.237.222.179])
by orsmga001.jf.intel.com with ESMTP; 11 Jan 2021 06:59:01 -0800
From: Anatoly Burakov <anatoly.burakov@intel.com>
To: dev@dpdk.org
Cc: Bruce Richardson <bruce.richardson@intel.com>,
Konstantin Ananyev <konstantin.ananyev@intel.com>, thomas@monjalon.net,
timothy.mcdaniel@intel.com, david.hunt@intel.com, chris.macnamara@intel.com
Date: Mon, 11 Jan 2021 14:58:47 +0000
Message-Id: <c5fe376170d48bfa3a85fede4369a67de023333d.1610377084.git.anatoly.burakov@intel.com>
X-Mailer: git-send-email 2.25.1
In-Reply-To: <cover.1610377084.git.anatoly.burakov@intel.com>
References: <cover.1610375528.git.anatoly.burakov@intel.com>
<cover.1610377084.git.anatoly.burakov@intel.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Subject: [dpdk-dev] [PATCH v15 02/11] eal: avoid invalid API usage in power
intrinsics
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/dev>,
<mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/dev>,
<mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
Sender: "dev" <dev-bounces@dpdk.org>
Currently, the API documentation mandates that if the user wants to use
the power management intrinsics, they need to call the
`rte_cpu_get_intrinsics_support` API and check support for specific
intrinsics.
However, if the user does not do that, it is possible to get illegal
instruction error because we're using raw instruction opcodes, which may
or may not be supported at runtime.
Now that we have everything in a C file, we can check for support at
startup and prevent the user from possibly encountering illegal
instruction errors.
Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
---
Notes:
v15:
- Remove accidental whitespace changes
v14:
- Replace uint8_t with bool
v14:
- Replace uint8_t with bool
.../include/generic/rte_power_intrinsics.h | 3 ---
lib/librte_eal/x86/rte_power_intrinsics.c | 25 +++++++++++++++++++
2 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/lib/librte_eal/include/generic/rte_power_intrinsics.h b/lib/librte_eal/include/generic/rte_power_intrinsics.h
index 67977bd511..ffa72f7578 100644
--- a/lib/librte_eal/include/generic/rte_power_intrinsics.h
+++ b/lib/librte_eal/include/generic/rte_power_intrinsics.h
@@ -34,7 +34,6 @@
*
* @warning It is responsibility of the user to check if this function is
* supported at runtime using `rte_cpu_get_intrinsics_support()` API call.
- * Failing to do so may result in an illegal CPU instruction error.
*
* @param p
* Address to monitor for changes.
@@ -75,7 +74,6 @@ void rte_power_monitor(const volatile void *p,
*
* @warning It is responsibility of the user to check if this function is
* supported at runtime using `rte_cpu_get_intrinsics_support()` API call.
- * Failing to do so may result in an illegal CPU instruction error.
*
* @param p
* Address to monitor for changes.
@@ -111,7 +109,6 @@ void rte_power_monitor_sync(const volatile void *p,
*
* @warning It is responsibility of the user to check if this function is
* supported at runtime using `rte_cpu_get_intrinsics_support()` API call.
- * Failing to do so may result in an illegal CPU instruction error.
*
* @param tsc_timestamp
* Maximum TSC timestamp to wait for. Note that the wait behavior is
diff --git a/lib/librte_eal/x86/rte_power_intrinsics.c b/lib/librte_eal/x86/rte_power_intrinsics.c
index 34c5fd9c3e..a164ad55fc 100644
--- a/lib/librte_eal/x86/rte_power_intrinsics.c
+++ b/lib/librte_eal/x86/rte_power_intrinsics.c
@@ -4,6 +4,8 @@
#include "rte_power_intrinsics.h"
+static bool wait_supported;
+
static inline uint64_t
__get_umwait_val(const volatile void *p, const uint8_t sz)
{
@@ -35,6 +37,11 @@ rte_power_monitor(const volatile void *p, const uint64_t expected_value,
{
const uint32_t tsc_l = (uint32_t)tsc_timestamp;
const uint32_t tsc_h = (uint32_t)(tsc_timestamp >> 32);
+
+ /* prevent user from running this instruction if it's not supported */
+ if (!wait_supported)
+ return;
+
/*
* we're using raw byte codes for now as only the newest compiler
* versions support this instruction natively.
@@ -72,6 +79,11 @@ rte_power_monitor_sync(const volatile void *p, const uint64_t expected_value,
{
const uint32_t tsc_l = (uint32_t)tsc_timestamp;
const uint32_t tsc_h = (uint32_t)(tsc_timestamp >> 32);
+
+ /* prevent user from running this instruction if it's not supported */
+ if (!wait_supported)
+ return;
+
/*
* we're using raw byte codes for now as only the newest compiler
* versions support this instruction natively.
@@ -112,9 +124,22 @@ rte_power_pause(const uint64_t tsc_timestamp)
const uint32_t tsc_l = (uint32_t)tsc_timestamp;
const uint32_t tsc_h = (uint32_t)(tsc_timestamp >> 32);
+ /* prevent user from running this instruction if it's not supported */
+ if (!wait_supported)
+ return;
+
/* execute TPAUSE */
asm volatile(".byte 0x66, 0x0f, 0xae, 0xf7;"
: /* ignore rflags */
: "D"(0), /* enter C0.2 */
"a"(tsc_l), "d"(tsc_h));
}
+
+RTE_INIT(rte_power_intrinsics_init) {
+ struct rte_cpu_intrinsics i;
+
+ rte_cpu_get_intrinsics_support(&i);
+
+ if (i.power_monitor && i.power_pause)
+ wait_supported = 1;
+}
--
2.25.1