[v1 0/7] DPAA2 crypto changes

[v1 0/7] DPAA2 crypto changes

[Gagandeep Singh]

Changes related to crypto driver

Gagandeep Singh (1):
  crypto/dpaa2_sec: fix memory leak

Jun Yang (5):
  crypto/dpaa2_sec: enhance IPsec RFLC handling
  crypto/dpaa2_sec: enhance pdcp FLC handling
  net/dpaa2: support FLC stashing API
  crypto/dpaa2_sec: remove prefetch code in event mode
  crypto/dpaa2_sec: rework debug code

Varun Sethi (1):
  common/dpaax: caamflib: fix PDCP SNOW-ZUC wdog DECO err

 drivers/bus/fslmc/portal/dpaa2_hw_pvt.h     |  44 ++++++
 drivers/common/dpaax/caamflib/desc/pdcp.h   |  10 ++
 drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 144 ++++++++++++--------
 drivers/net/dpaa2/dpaa2_ethdev.c            |  25 ++--
 4 files changed, 153 insertions(+), 70 deletions(-)

-- 
2.25.1

[v1 1/7] crypto/dpaa2_sec: fix memory leak

[Gagandeep Singh]

fixing memory leak while creating the PDCP session
with invalid data.

Fixes: bef594ec5cc8 ("crypto/dpaa2_sec: support PDCP offload")
Cc: akhil.goyal@nxp.com
Cc: stable@dpdk.org

Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
---
 drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
index c1f7181d55..e0b8bacdb8 100644
--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
@@ -3420,6 +3420,7 @@ dpaa2_sec_set_pdcp_session(struct rte_cryptodev *dev,
 		}
 	} else {
 		DPAA2_SEC_ERR("Invalid crypto type");
+		rte_free(priv);
 		return -EINVAL;
 	}
 
-- 
2.25.1

[v1 2/7] common/dpaax: caamflib: fix PDCP SNOW-ZUC wdog DECO err

[Gagandeep Singh]

From: Varun Sethi <v.sethi@nxp.com>

Adding a Jump instruction with CALM flag to ensure
previous processing has been completed.

Fixes: 8827d94398f1 ("crypto/dpaa2_sec/hw: support AES-AES 18-bit PDCP")
Cc: vakul.garg@nxp.com
Cc: stable@dpdk.org

Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Signed-off-by: Varun Sethi <v.sethi@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
 drivers/common/dpaax/caamflib/desc/pdcp.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/common/dpaax/caamflib/desc/pdcp.h b/drivers/common/dpaax/caamflib/desc/pdcp.h
index bc35114cf4..9ada3905c5 100644
--- a/drivers/common/dpaax/caamflib/desc/pdcp.h
+++ b/drivers/common/dpaax/caamflib/desc/pdcp.h
@@ -1220,6 +1220,11 @@ pdcp_insert_cplane_snow_aes_op(struct program *p,
 		SEQFIFOLOAD(p, MSG1, 0, VLF | LAST1 | FLUSH1);
 		MOVEB(p, CONTEXT1, 0, MATH3, 0, 4, WAITCOMP | IMMED);
 
+		/* conditional jump with calm added to ensure that the
+		 * previous processing has been completed
+		 */
+		JUMP(p, 1, LOCAL_JUMP, ALL_TRUE, CALM);
+
 		LOAD(p, CLRW_RESET_CLS1_CHA |
 		     CLRW_CLR_C1KEY |
 		     CLRW_CLR_C1CTX |
@@ -1921,6 +1926,11 @@ pdcp_insert_cplane_zuc_aes_op(struct program *p,
 
 		MOVEB(p, OFIFO, 0, MATH3, 0, 4, IMMED);
 
+		/* conditional jump with calm added to ensure that the
+		 * previous processing has been completed
+		 */
+		JUMP(p, 1, LOCAL_JUMP, ALL_TRUE, CALM);
+
 		LOAD(p, CLRW_RESET_CLS1_CHA |
 		     CLRW_CLR_C1KEY |
 		     CLRW_CLR_C1CTX |
-- 
2.25.1

[v1 3/7] crypto/dpaa2_sec: enhance IPsec RFLC handling

[Gagandeep Singh]

From: Jun Yang <jun.yang@nxp.com>

Point Response FLC to FLC(SEC descriptor context).
Response FLC can be used for debug purpose in dequeue process.
Enable data stashing only. Annotation stashing is disabled which
is not suitable for SEC and impacts performance.

Signed-off-by: Jun Yang <jun.yang@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
 drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 44 ++++++++++++---------
 1 file changed, 26 insertions(+), 18 deletions(-)

diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
index e0b8bacdb8..0e30192b30 100644
--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
@@ -2005,7 +2005,7 @@ dpaa2_sec_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
 	struct fsl_mc_io *dpseci = (struct fsl_mc_io *)priv->hw;
 	struct dpseci_rx_queue_cfg cfg;
 	int32_t retcode;
-	char str[30];
+	char str[RTE_MEMZONE_NAMESIZE];
 
 	PMD_INIT_FUNC_TRACE();
 
@@ -2065,8 +2065,7 @@ dpaa2_sec_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
 		return -ENOMEM;
 	}
 
-	cfg.options = cfg.options | DPSECI_QUEUE_OPT_USER_CTX;
-	cfg.user_ctx = (size_t)(&qp->rx_vq);
+	cfg.dest_cfg.dest_type = DPSECI_DEST_NONE;
 	retcode = dpseci_set_rx_queue(dpseci, CMD_PRI_LOW, priv->token,
 				      qp_id, &cfg);
 	return retcode;
@@ -3060,14 +3059,19 @@ dpaa2_sec_set_ipsec_session(struct rte_cryptodev *dev,
 	struct alginfo authdata, cipherdata;
 	int bufsize;
 	struct sec_flow_context *flc;
+	uint64_t flc_iova;
 	int ret = -1;
 
 	PMD_INIT_FUNC_TRACE();
 
-	priv = (struct ctxt_priv *)rte_zmalloc(NULL,
-				sizeof(struct ctxt_priv) +
-				sizeof(struct sec_flc_desc),
-				RTE_CACHE_LINE_SIZE);
+	RTE_SET_USED(dev);
+
+	/** Make FLC address to align with stashing, low 6 bits are used
+	 * control stashing.
+	 */
+	priv = rte_zmalloc(NULL, sizeof(struct ctxt_priv) +
+		sizeof(struct sec_flc_desc),
+		DPAA2_STASHING_ALIGN_SIZE);
 
 	if (priv == NULL) {
 		DPAA2_SEC_ERR("No memory for priv CTXT");
@@ -3077,10 +3081,12 @@ dpaa2_sec_set_ipsec_session(struct rte_cryptodev *dev,
 	flc = &priv->flc_desc[0].flc;
 
 	if (ipsec_xform->life.bytes_hard_limit != 0 ||
-	    ipsec_xform->life.bytes_soft_limit != 0 ||
-	    ipsec_xform->life.packets_hard_limit != 0 ||
-	    ipsec_xform->life.packets_soft_limit != 0)
+		ipsec_xform->life.bytes_soft_limit != 0 ||
+		ipsec_xform->life.packets_hard_limit != 0 ||
+		ipsec_xform->life.packets_soft_limit != 0) {
+		rte_free(priv);
 		return -ENOTSUP;
+	}
 
 	memset(session, 0, sizeof(dpaa2_sec_session));
 
@@ -3330,24 +3336,26 @@ dpaa2_sec_set_ipsec_session(struct rte_cryptodev *dev,
 				1, 0, (rta_sec_era >= RTA_SEC_ERA_10) ?
 				SHR_WAIT : SHR_SERIAL,
 				&decap_pdb, &cipherdata, &authdata);
-	} else
+	} else {
+		ret = -EINVAL;
 		goto out;
+	}
 
 	if (bufsize < 0) {
+		ret = -EINVAL;
 		DPAA2_SEC_ERR("Crypto: Invalid SEC-DESC buffer length");
 		goto out;
 	}
 
 	flc->word1_sdl = (uint8_t)bufsize;
 
-	/* Enable the stashing control bit */
+	flc_iova = DPAA2_VADDR_TO_IOVA(flc);
+	/* Enable the stashing control bit and data stashing only.*/
 	DPAA2_SET_FLC_RSC(flc);
-	flc->word2_rflc_31_0 = lower_32_bits(
-			(size_t)&(((struct dpaa2_sec_qp *)
-			dev->data->queue_pairs[0])->rx_vq) | 0x14);
-	flc->word3_rflc_63_32 = upper_32_bits(
-			(size_t)&(((struct dpaa2_sec_qp *)
-			dev->data->queue_pairs[0])->rx_vq));
+	dpaa2_flc_stashing_set(DPAA2_FLC_DATA_STASHING, 1,
+		&flc_iova);
+	flc->word2_rflc_31_0 = lower_32_bits(flc_iova);
+	flc->word3_rflc_63_32 = upper_32_bits(flc_iova);
 
 	/* Set EWS bit i.e. enable write-safe */
 	DPAA2_SET_FLC_EWS(flc);
-- 
2.25.1

[v1 4/7] crypto/dpaa2_sec: enhance pdcp FLC handling

[Gagandeep Singh]

From: Jun Yang <jun.yang@nxp.com>

Set RFLC with FLC IOVA address and data stashing only.

Signed-off-by: Jun Yang <jun.yang@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
 drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
index 0e30192b30..ff24a8919a 100644
--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
@@ -3389,6 +3389,7 @@ dpaa2_sec_set_pdcp_session(struct rte_cryptodev *dev,
 	struct alginfo *p_authdata = NULL;
 	int bufsize = -1;
 	struct sec_flow_context *flc;
+	uint64_t flc_iova;
 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
 	int swap = true;
 #else
@@ -3397,6 +3398,8 @@ dpaa2_sec_set_pdcp_session(struct rte_cryptodev *dev,
 
 	PMD_INIT_FUNC_TRACE();
 
+	RTE_SET_USED(dev);
+
 	memset(session, 0, sizeof(dpaa2_sec_session));
 
 	priv = (struct ctxt_priv *)rte_zmalloc(NULL,
@@ -3646,14 +3649,13 @@ dpaa2_sec_set_pdcp_session(struct rte_cryptodev *dev,
 		goto out;
 	}
 
-	/* Enable the stashing control bit */
+	flc_iova = DPAA2_VADDR_TO_IOVA(flc);
+	/* Enable the stashing control bit and data stashing only.*/
 	DPAA2_SET_FLC_RSC(flc);
-	flc->word2_rflc_31_0 = lower_32_bits(
-			(size_t)&(((struct dpaa2_sec_qp *)
-			dev->data->queue_pairs[0])->rx_vq) | 0x14);
-	flc->word3_rflc_63_32 = upper_32_bits(
-			(size_t)&(((struct dpaa2_sec_qp *)
-			dev->data->queue_pairs[0])->rx_vq));
+	dpaa2_flc_stashing_set(DPAA2_FLC_DATA_STASHING, 1,
+		&flc_iova);
+	flc->word2_rflc_31_0 = lower_32_bits(flc_iova);
+	flc->word3_rflc_63_32 = upper_32_bits(flc_iova);
 
 	flc->word1_sdl = (uint8_t)bufsize;
 
-- 
2.25.1

[v1 5/7] net/dpaa2: support FLC stashing API

[Gagandeep Singh]

From: Jun Yang <jun.yang@nxp.com>

Configure flow steering action with FLC enabled to align stashing
setting with RSS configuration.

Signed-off-by: Jun Yang <jun.yang@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
 drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 44 +++++++++++++++++++++++++
 drivers/net/dpaa2/dpaa2_ethdev.c        | 25 +++++++-------
 2 files changed, 58 insertions(+), 11 deletions(-)

diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
index 169c7917ea..4c30e6db18 100644
--- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
@@ -179,6 +179,7 @@ struct __rte_cache_aligned dpaa2_queue {
 	uint16_t resv;
 	uint64_t offloads;
 	uint64_t lpbk_cntx;
+	uint8_t data_stashing_off;
 };
 
 struct swp_active_dqs {
@@ -463,6 +464,49 @@ struct qbman_result *get_swp_active_dqs(uint16_t dpio_index)
 	return rte_global_active_dqs_list[dpio_index].global_active_dqs;
 }
 
+/* 00 00 00 - last 6 bit represent data, annotation,
+ * context stashing setting 01 01 00 (0x14)
+ * (in following order ->DS AS CS)
+ * to enable 1 line data, 1 line annotation.
+ * For LX2, this setting should be 01 00 00 (0x10)
+ */
+#define DPAA2_FLC_STASHING_MAX_BIT_SIZE 2
+#define DPAA2_FLC_STASHING_MAX_CACHE_LINE \
+	((1ULL << DPAA2_FLC_STASHING_MAX_BIT_SIZE) - 1)
+
+enum dpaa2_flc_stashing_type {
+	DPAA2_FLC_CNTX_STASHING = 0,
+	DPAA2_FLC_ANNO_STASHING =
+		DPAA2_FLC_CNTX_STASHING + DPAA2_FLC_STASHING_MAX_BIT_SIZE,
+	DPAA2_FLC_DATA_STASHING =
+		DPAA2_FLC_ANNO_STASHING + DPAA2_FLC_STASHING_MAX_BIT_SIZE,
+	DPAA2_FLC_END_STASHING =
+		DPAA2_FLC_DATA_STASHING + DPAA2_FLC_STASHING_MAX_BIT_SIZE
+};
+
+#define DPAA2_STASHING_ALIGN_SIZE (1 << DPAA2_FLC_END_STASHING)
+
+static inline void
+dpaa2_flc_stashing_set(enum dpaa2_flc_stashing_type type,
+	uint8_t cache_line, uint64_t *flc)
+{
+	RTE_ASSERT(cache_line <= DPAA2_FLC_STASHING_MAX_CACHE_LINE);
+	RTE_ASSERT(type == DPAA2_FLC_CNTX_STASHING ||
+		type == DPAA2_FLC_ANNO_STASHING ||
+		type == DPAA2_FLC_DATA_STASHING);
+
+	(*flc) &= ~(DPAA2_FLC_STASHING_MAX_CACHE_LINE << type);
+	(*flc) |= (cache_line << type);
+}
+
+static inline void
+dpaa2_flc_stashing_clear_all(uint64_t *flc)
+{
+	dpaa2_flc_stashing_set(DPAA2_FLC_CNTX_STASHING, 0, flc);
+	dpaa2_flc_stashing_set(DPAA2_FLC_ANNO_STASHING, 0, flc);
+	dpaa2_flc_stashing_set(DPAA2_FLC_DATA_STASHING, 0, flc);
+}
+
 static inline
 void set_swp_active_dqs(uint16_t dpio_index, struct qbman_result *dqs)
 {
diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c
index 449bbda7ca..726bc0cf3e 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.c
+++ b/drivers/net/dpaa2/dpaa2_ethdev.c
@@ -786,17 +786,20 @@ dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
 	if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
 		options |= DPNI_QUEUE_OPT_FLC;
 		cfg.flc.stash_control = true;
-		cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
-		/* 00 00 00 - last 6 bit represent annotation, context stashing,
-		 * data stashing setting 01 01 00 (0x14)
-		 * (in following order ->DS AS CS)
-		 * to enable 1 line data, 1 line annotation.
-		 * For LX2, this setting should be 01 00 00 (0x10)
-		 */
-		if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
-			cfg.flc.value |= 0x10;
-		else
-			cfg.flc.value |= 0x14;
+		dpaa2_flc_stashing_clear_all(&cfg.flc.value);
+		if (getenv("DPAA2_DATA_STASHING_OFF")) {
+			dpaa2_flc_stashing_set(DPAA2_FLC_DATA_STASHING, 0,
+				&cfg.flc.value);
+			dpaa2_q->data_stashing_off = 1;
+		} else {
+			dpaa2_flc_stashing_set(DPAA2_FLC_DATA_STASHING, 1,
+				&cfg.flc.value);
+			dpaa2_q->data_stashing_off = 0;
+		}
+		if ((dpaa2_svr_family & 0xffff0000) != SVR_LX2160A) {
+			dpaa2_flc_stashing_set(DPAA2_FLC_ANNO_STASHING, 1,
+				&cfg.flc.value);
+		}
 	}
 	ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
 			     dpaa2_q->tc_index, flow_id, options, &cfg);
-- 
2.25.1

Re: [v1 5/7] net/dpaa2: support FLC stashing API

[Hemant Agrawal]

Hi Gagan,


I think this patch shall come before the 4th patch:   [v1 4/7] 
crypto/dpaa2_sec: enhance pdcp FLC handling


- Hemant


On 06-08-2024 14:11, Gagandeep Singh wrote:
> From: Jun Yang <jun.yang@nxp.com>
>
> Configure flow steering action with FLC enabled to align stashing
> setting with RSS configuration.
>
> Signed-off-by: Jun Yang <jun.yang@nxp.com>
> Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
> ---
>   drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 44 +++++++++++++++++++++++++
>   drivers/net/dpaa2/dpaa2_ethdev.c        | 25 +++++++-------
>   2 files changed, 58 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
> index 169c7917ea..4c30e6db18 100644
> --- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
> +++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
> @@ -179,6 +179,7 @@ struct __rte_cache_aligned dpaa2_queue {
>   	uint16_t resv;
>   	uint64_t offloads;
>   	uint64_t lpbk_cntx;
> +	uint8_t data_stashing_off;
>   };
>   
>   struct swp_active_dqs {
> @@ -463,6 +464,49 @@ struct qbman_result *get_swp_active_dqs(uint16_t dpio_index)
>   	return rte_global_active_dqs_list[dpio_index].global_active_dqs;
>   }
>   
> +/* 00 00 00 - last 6 bit represent data, annotation,
> + * context stashing setting 01 01 00 (0x14)
> + * (in following order ->DS AS CS)
> + * to enable 1 line data, 1 line annotation.
> + * For LX2, this setting should be 01 00 00 (0x10)
> + */
> +#define DPAA2_FLC_STASHING_MAX_BIT_SIZE 2
> +#define DPAA2_FLC_STASHING_MAX_CACHE_LINE \
> +	((1ULL << DPAA2_FLC_STASHING_MAX_BIT_SIZE) - 1)
> +
> +enum dpaa2_flc_stashing_type {
> +	DPAA2_FLC_CNTX_STASHING = 0,
> +	DPAA2_FLC_ANNO_STASHING =
> +		DPAA2_FLC_CNTX_STASHING + DPAA2_FLC_STASHING_MAX_BIT_SIZE,
> +	DPAA2_FLC_DATA_STASHING =
> +		DPAA2_FLC_ANNO_STASHING + DPAA2_FLC_STASHING_MAX_BIT_SIZE,
> +	DPAA2_FLC_END_STASHING =
> +		DPAA2_FLC_DATA_STASHING + DPAA2_FLC_STASHING_MAX_BIT_SIZE
> +};
> +
> +#define DPAA2_STASHING_ALIGN_SIZE (1 << DPAA2_FLC_END_STASHING)
> +
> +static inline void
> +dpaa2_flc_stashing_set(enum dpaa2_flc_stashing_type type,
> +	uint8_t cache_line, uint64_t *flc)
> +{
> +	RTE_ASSERT(cache_line <= DPAA2_FLC_STASHING_MAX_CACHE_LINE);
> +	RTE_ASSERT(type == DPAA2_FLC_CNTX_STASHING ||
> +		type == DPAA2_FLC_ANNO_STASHING ||
> +		type == DPAA2_FLC_DATA_STASHING);
> +
> +	(*flc) &= ~(DPAA2_FLC_STASHING_MAX_CACHE_LINE << type);
> +	(*flc) |= (cache_line << type);
> +}
> +
> +static inline void
> +dpaa2_flc_stashing_clear_all(uint64_t *flc)
> +{
> +	dpaa2_flc_stashing_set(DPAA2_FLC_CNTX_STASHING, 0, flc);
> +	dpaa2_flc_stashing_set(DPAA2_FLC_ANNO_STASHING, 0, flc);
> +	dpaa2_flc_stashing_set(DPAA2_FLC_DATA_STASHING, 0, flc);
> +}
> +
>   static inline
>   void set_swp_active_dqs(uint16_t dpio_index, struct qbman_result *dqs)
>   {
> diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c
> index 449bbda7ca..726bc0cf3e 100644
> --- a/drivers/net/dpaa2/dpaa2_ethdev.c
> +++ b/drivers/net/dpaa2/dpaa2_ethdev.c
> @@ -786,17 +786,20 @@ dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
>   	if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
>   		options |= DPNI_QUEUE_OPT_FLC;
>   		cfg.flc.stash_control = true;
> -		cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
> -		/* 00 00 00 - last 6 bit represent annotation, context stashing,
> -		 * data stashing setting 01 01 00 (0x14)
> -		 * (in following order ->DS AS CS)
> -		 * to enable 1 line data, 1 line annotation.
> -		 * For LX2, this setting should be 01 00 00 (0x10)
> -		 */
> -		if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
> -			cfg.flc.value |= 0x10;
> -		else
> -			cfg.flc.value |= 0x14;
> +		dpaa2_flc_stashing_clear_all(&cfg.flc.value);
> +		if (getenv("DPAA2_DATA_STASHING_OFF")) {
> +			dpaa2_flc_stashing_set(DPAA2_FLC_DATA_STASHING, 0,
> +				&cfg.flc.value);
> +			dpaa2_q->data_stashing_off = 1;
> +		} else {
> +			dpaa2_flc_stashing_set(DPAA2_FLC_DATA_STASHING, 1,
> +				&cfg.flc.value);
> +			dpaa2_q->data_stashing_off = 0;
> +		}
> +		if ((dpaa2_svr_family & 0xffff0000) != SVR_LX2160A) {
> +			dpaa2_flc_stashing_set(DPAA2_FLC_ANNO_STASHING, 1,
> +				&cfg.flc.value);
> +		}
>   	}
>   	ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
>   			     dpaa2_q->tc_index, flow_id, options, &cfg);

[v1 6/7] crypto/dpaa2_sec: remove prefetch code in event mode

[Gagandeep Singh]

From: Jun Yang <jun.yang@nxp.com>

Should not prefetch mbuf and crypto_op which are not touched
by hardware.

Signed-off-by: Jun Yang <jun.yang@nxp.com>
---
 drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 20 +-------------------
 1 file changed, 1 insertion(+), 19 deletions(-)

diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
index ff24a8919a..1e28c71b53 100644
--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
@@ -3991,12 +3991,6 @@ dpaa2_sec_process_parallel_event(struct qbman_swp *swp,
 				 struct rte_event *ev)
 {
 	struct dpaa2_sec_qp *qp;
-	/* Prefetching mbuf */
-	rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd)-
-		rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size));
-
-	/* Prefetching ipsec crypto_op stored in priv data of mbuf */
-	rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd)-64));
 
 	qp = container_of(rxq, struct dpaa2_sec_qp, rx_vq);
 	ev->flow_id = rxq->ev.flow_id;
@@ -4010,6 +4004,7 @@ dpaa2_sec_process_parallel_event(struct qbman_swp *swp,
 
 	qbman_swp_dqrr_consume(swp, dq);
 }
+
 static void
 dpaa2_sec_process_atomic_event(struct qbman_swp *swp __rte_unused,
 				 const struct qbman_fd *fd,
@@ -4020,12 +4015,6 @@ dpaa2_sec_process_atomic_event(struct qbman_swp *swp __rte_unused,
 	uint8_t dqrr_index;
 	struct dpaa2_sec_qp *qp;
 	struct rte_crypto_op *crypto_op;
-	/* Prefetching mbuf */
-	rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd)-
-		rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size));
-
-	/* Prefetching ipsec crypto_op stored in priv data of mbuf */
-	rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd)-64));
 
 	qp = container_of(rxq, struct dpaa2_sec_qp, rx_vq);
 	ev->flow_id = rxq->ev.flow_id;
@@ -4055,13 +4044,6 @@ dpaa2_sec_process_ordered_event(struct qbman_swp *swp,
 	struct rte_crypto_op *crypto_op;
 	struct dpaa2_sec_qp *qp;
 
-	/* Prefetching mbuf */
-	rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd)-
-		rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size));
-
-	/* Prefetching ipsec crypto_op stored in priv data of mbuf */
-	rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd)-64));
-
 	qp = container_of(rxq, struct dpaa2_sec_qp, rx_vq);
 	ev->flow_id = rxq->ev.flow_id;
 	ev->sub_event_type = rxq->ev.sub_event_type;
-- 
2.25.1

[v1 7/7] crypto/dpaa2_sec: rework debug code

[Gagandeep Singh]

From: Jun Yang <jun.yang@nxp.com>

Output debug information according to various modes.

Signed-off-by: Jun Yang <jun.yang@nxp.com>
---
 drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 63 ++++++++++++++++-----
 1 file changed, 48 insertions(+), 15 deletions(-)

diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
index 1e28c71b53..da3bd871ba 100644
--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
@@ -1095,7 +1095,7 @@ build_auth_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
 
 static int
 build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
-		struct qbman_fd *fd, __rte_unused uint16_t bpid)
+		struct qbman_fd *fd, uint16_t bpid)
 {
 	struct rte_crypto_sym_op *sym_op = op->sym;
 	struct qbman_fle *ip_fle, *op_fle, *sge, *fle;
@@ -1105,6 +1105,10 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
 	struct rte_mbuf *mbuf;
 	uint8_t *iv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,
 			sess->iv.offset);
+#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
+	char debug_str[1024];
+	int offset;
+#endif
 
 	data_len = sym_op->cipher.data.length;
 	data_offset = sym_op->cipher.data.offset;
@@ -1210,14 +1214,26 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
 	DPAA2_SET_FD_COMPOUND_FMT(fd);
 	DPAA2_SET_FD_FLC(fd, DPAA2_VADDR_TO_IOVA(flc));
 
-	DPAA2_SEC_DP_DEBUG(
-		"CIPHER SG: fdaddr =%" PRIx64 " bpid =%d meta =%d"
-		" off =%d, len =%d\n",
+#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
+	offset = sprintf(debug_str,
+		"CIPHER SG: fdaddr =%" PRIx64 ", from %s pool ",
 		DPAA2_GET_FD_ADDR(fd),
-		DPAA2_GET_FD_BPID(fd),
-		rte_dpaa2_bpid_info[bpid].meta_data_size,
-		DPAA2_GET_FD_OFFSET(fd),
-		DPAA2_GET_FD_LEN(fd));
+		bpid < MAX_BPID ? "SW" : "BMAN");
+	if (bpid < MAX_BPID) {
+		offset += sprintf(&debug_str[offset],
+			"bpid = %d ", bpid);
+	}
+	offset += sprintf(&debug_str[offset],
+		"private size = %d ",
+		mbuf->pool->private_data_size);
+	offset += sprintf(&debug_str[offset],
+		"off =%d, len =%d\n",
+		DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_LEN(fd));
+		DPAA2_SEC_DP_DEBUG("%s", debug_str);
+#else
+	RTE_SET_USED(bpid);
+#endif
+
 	return 0;
 }
 
@@ -1233,6 +1249,10 @@ build_cipher_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
 	uint8_t *iv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,
 			sess->iv.offset);
 	struct rte_mbuf *dst;
+#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
+	char debug_str[1024];
+	int offset;
+#endif
 
 	data_len = sym_op->cipher.data.length;
 	data_offset = sym_op->cipher.data.offset;
@@ -1324,14 +1344,23 @@ build_cipher_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
 	DPAA2_SET_FLE_FIN(sge);
 	DPAA2_SET_FLE_FIN(fle);
 
-	DPAA2_SEC_DP_DEBUG(
-		"CIPHER: fdaddr =%" PRIx64 " bpid =%d meta =%d"
-		" off =%d, len =%d\n",
+#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
+	offset = sprintf(debug_str,
+		"CIPHER: fdaddr =%" PRIx64 ", from %s pool ",
 		DPAA2_GET_FD_ADDR(fd),
-		DPAA2_GET_FD_BPID(fd),
-		rte_dpaa2_bpid_info[bpid].meta_data_size,
-		DPAA2_GET_FD_OFFSET(fd),
-		DPAA2_GET_FD_LEN(fd));
+		bpid < MAX_BPID ? "SW" : "BMAN");
+	if (bpid < MAX_BPID) {
+		offset += sprintf(&debug_str[offset],
+			"bpid = %d ", bpid);
+	}
+	offset += sprintf(&debug_str[offset],
+			"private size = %d ",
+			dst->pool->private_data_size);
+	offset += sprintf(&debug_str[offset],
+			"off =%d, len =%d\n",
+			DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_LEN(fd));
+	DPAA2_SEC_DP_DEBUG("%s", debug_str);
+#endif
 
 	return 0;
 }
@@ -1564,6 +1593,10 @@ sec_fd_to_mbuf(const struct qbman_fd *fd, struct dpaa2_sec_qp *qp)
 	struct qbman_fle *fle;
 	struct rte_crypto_op *op;
 	struct rte_mbuf *dst, *src;
+#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
+	char debug_str[1024];
+	int offset;
+#endif
 
 	if (DPAA2_FD_GET_FORMAT(fd) == qbman_fd_single)
 		return sec_simple_fd_to_mbuf(fd);
-- 
2.25.1

Re: [v1 7/7] crypto/dpaa2_sec: rework debug code

[Hemant Agrawal]

Hi Gagan,

On 06-08-2024 14:11, Gagandeep Singh wrote:
> From: Jun Yang <jun.yang@nxp.com>
>
> Output debug information according to various modes.
>
> Signed-off-by: Jun Yang <jun.yang@nxp.com>
> ---
>   drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 63 ++++++++++++++++-----
>   1 file changed, 48 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
> index 1e28c71b53..da3bd871ba 100644
> --- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
> +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
> @@ -1095,7 +1095,7 @@ build_auth_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
>   
>   static int
>   build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
> -		struct qbman_fd *fd, __rte_unused uint16_t bpid)
> +		struct qbman_fd *fd, uint16_t bpid)
>   {
>   	struct rte_crypto_sym_op *sym_op = op->sym;
>   	struct qbman_fle *ip_fle, *op_fle, *sge, *fle;
> @@ -1105,6 +1105,10 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
>   	struct rte_mbuf *mbuf;
>   	uint8_t *iv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,
>   			sess->iv.offset);
> +#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
> +	char debug_str[1024];
> +	int offset;
> +#endif
>   
>   	data_len = sym_op->cipher.data.length;
>   	data_offset = sym_op->cipher.data.offset;
> @@ -1210,14 +1214,26 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
>   	DPAA2_SET_FD_COMPOUND_FMT(fd);
>   	DPAA2_SET_FD_FLC(fd, DPAA2_VADDR_TO_IOVA(flc));
>   
> -	DPAA2_SEC_DP_DEBUG(
> -		"CIPHER SG: fdaddr =%" PRIx64 " bpid =%d meta =%d"
> -		" off =%d, len =%d\n",
> +#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
> +	offset = sprintf(debug_str,
> +		"CIPHER SG: fdaddr =%" PRIx64 ", from %s pool ",
>   		DPAA2_GET_FD_ADDR(fd),
> -		DPAA2_GET_FD_BPID(fd),
> -		rte_dpaa2_bpid_info[bpid].meta_data_size,
> -		DPAA2_GET_FD_OFFSET(fd),
> -		DPAA2_GET_FD_LEN(fd));
> +		bpid < MAX_BPID ? "SW" : "BMAN");
> +	if (bpid < MAX_BPID) {
> +		offset += sprintf(&debug_str[offset],
> +			"bpid = %d ", bpid);
> +	}
> +	offset += sprintf(&debug_str[offset],
> +		"private size = %d ",
> +		mbuf->pool->private_data_size);
> +	offset += sprintf(&debug_str[offset],
> +		"off =%d, len =%d\n",
> +		DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_LEN(fd));
> +		DPAA2_SEC_DP_DEBUG("%s", debug_str);
> +#else
> +	RTE_SET_USED(bpid);
> +#endif
> +
>   	return 0;
>   }
>   
> @@ -1233,6 +1249,10 @@ build_cipher_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
>   	uint8_t *iv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,
>   			sess->iv.offset);
>   	struct rte_mbuf *dst;
> +#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
> +	char debug_str[1024];
> +	int offset;
> +#endif
>   
>   	data_len = sym_op->cipher.data.length;
>   	data_offset = sym_op->cipher.data.offset;
> @@ -1324,14 +1344,23 @@ build_cipher_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
>   	DPAA2_SET_FLE_FIN(sge);
>   	DPAA2_SET_FLE_FIN(fle);
>   
> -	DPAA2_SEC_DP_DEBUG(
> -		"CIPHER: fdaddr =%" PRIx64 " bpid =%d meta =%d"
> -		" off =%d, len =%d\n",
> +#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
> +	offset = sprintf(debug_str,
> +		"CIPHER: fdaddr =%" PRIx64 ", from %s pool ",
>   		DPAA2_GET_FD_ADDR(fd),
> -		DPAA2_GET_FD_BPID(fd),
> -		rte_dpaa2_bpid_info[bpid].meta_data_size,
> -		DPAA2_GET_FD_OFFSET(fd),
> -		DPAA2_GET_FD_LEN(fd));
> +		bpid < MAX_BPID ? "SW" : "BMAN");
> +	if (bpid < MAX_BPID) {
> +		offset += sprintf(&debug_str[offset],
> +			"bpid = %d ", bpid);
> +	}
> +	offset += sprintf(&debug_str[offset],
> +			"private size = %d ",
> +			dst->pool->private_data_size);
> +	offset += sprintf(&debug_str[offset],
> +			"off =%d, len =%d\n",
> +			DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_LEN(fd));
> +	DPAA2_SEC_DP_DEBUG("%s", debug_str);
> +#endif
>   
>   	return 0;
>   }
> @@ -1564,6 +1593,10 @@ sec_fd_to_mbuf(const struct qbman_fd *fd, struct dpaa2_sec_qp *qp)
>   	struct qbman_fle *fle;
>   	struct rte_crypto_op *op;
>   	struct rte_mbuf *dst, *src;
> +#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
> +	char debug_str[1024];
> +	int offset;
> +#endif

you have defined these variables but not used?  have you missed 
something in this patch?


>   
>   	if (DPAA2_FD_GET_FORMAT(fd) == qbman_fd_single)
>   		return sec_simple_fd_to_mbuf(fd);

[v2 0/7] DPAA2 crypto changes

[Gagandeep Singh]

v2 changes:
	* fix patch sequence
	* add missing code in
	"crypto/dpaa2_sec: rework debug code"

Changes related to crypto driver

Gagandeep Singh (1):
  crypto/dpaa2_sec: fix memory leak

Jun Yang (5):
  net/dpaa2: support FLC stashing API
  crypto/dpaa2_sec: enhance IPsec RFLC handling
  crypto/dpaa2_sec: enhance pdcp FLC handling
  crypto/dpaa2_sec: remove prefetch code in event mode
  crypto/dpaa2_sec: rework debug code

Varun Sethi (1):
  common/dpaax: caamflib: fix PDCP SNOW-ZUC wdog DECO err

 drivers/bus/fslmc/portal/dpaa2_hw_pvt.h     |  44 +++++
 drivers/common/dpaax/caamflib/desc/pdcp.h   |  10 ++
 drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 168 ++++++++++++--------
 drivers/net/dpaa2/dpaa2_ethdev.c            |  25 +--
 4 files changed, 168 insertions(+), 79 deletions(-)

-- 
2.25.1

[v2 1/7] crypto/dpaa2_sec: fix memory leak

[Gagandeep Singh]

fixing memory leak while creating the PDCP session
with invalid data.

Fixes: bef594ec5cc8 ("crypto/dpaa2_sec: support PDCP offload")
Cc: akhil.goyal@nxp.com
Cc: stable@dpdk.org

Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
---
 drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
index c1f7181d55..e0b8bacdb8 100644
--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
@@ -3420,6 +3420,7 @@ dpaa2_sec_set_pdcp_session(struct rte_cryptodev *dev,
 		}
 	} else {
 		DPAA2_SEC_ERR("Invalid crypto type");
+		rte_free(priv);
 		return -EINVAL;
 	}
 
-- 
2.25.1

[v2 2/7] common/dpaax: caamflib: fix PDCP SNOW-ZUC wdog DECO err

[Gagandeep Singh]

From: Varun Sethi <v.sethi@nxp.com>

Adding a Jump instruction with CALM flag to ensure
previous processing has been completed.

Fixes: 8827d94398f1 ("crypto/dpaa2_sec/hw: support AES-AES 18-bit PDCP")
Cc: vakul.garg@nxp.com
Cc: stable@dpdk.org

Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Signed-off-by: Varun Sethi <v.sethi@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
 drivers/common/dpaax/caamflib/desc/pdcp.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/common/dpaax/caamflib/desc/pdcp.h b/drivers/common/dpaax/caamflib/desc/pdcp.h
index bc35114cf4..9ada3905c5 100644
--- a/drivers/common/dpaax/caamflib/desc/pdcp.h
+++ b/drivers/common/dpaax/caamflib/desc/pdcp.h
@@ -1220,6 +1220,11 @@ pdcp_insert_cplane_snow_aes_op(struct program *p,
 		SEQFIFOLOAD(p, MSG1, 0, VLF | LAST1 | FLUSH1);
 		MOVEB(p, CONTEXT1, 0, MATH3, 0, 4, WAITCOMP | IMMED);
 
+		/* conditional jump with calm added to ensure that the
+		 * previous processing has been completed
+		 */
+		JUMP(p, 1, LOCAL_JUMP, ALL_TRUE, CALM);
+
 		LOAD(p, CLRW_RESET_CLS1_CHA |
 		     CLRW_CLR_C1KEY |
 		     CLRW_CLR_C1CTX |
@@ -1921,6 +1926,11 @@ pdcp_insert_cplane_zuc_aes_op(struct program *p,
 
 		MOVEB(p, OFIFO, 0, MATH3, 0, 4, IMMED);
 
+		/* conditional jump with calm added to ensure that the
+		 * previous processing has been completed
+		 */
+		JUMP(p, 1, LOCAL_JUMP, ALL_TRUE, CALM);
+
 		LOAD(p, CLRW_RESET_CLS1_CHA |
 		     CLRW_CLR_C1KEY |
 		     CLRW_CLR_C1CTX |
-- 
2.25.1

[v2 3/7] net/dpaa2: support FLC stashing API

[Gagandeep Singh]

From: Jun Yang <jun.yang@nxp.com>

Configure flow steering action with FLC enabled to align stashing
setting with RSS configuration.

Signed-off-by: Jun Yang <jun.yang@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
 drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 44 +++++++++++++++++++++++++
 drivers/net/dpaa2/dpaa2_ethdev.c        | 25 +++++++-------
 2 files changed, 58 insertions(+), 11 deletions(-)

diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
index 169c7917ea..4c30e6db18 100644
--- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
@@ -179,6 +179,7 @@ struct __rte_cache_aligned dpaa2_queue {
 	uint16_t resv;
 	uint64_t offloads;
 	uint64_t lpbk_cntx;
+	uint8_t data_stashing_off;
 };
 
 struct swp_active_dqs {
@@ -463,6 +464,49 @@ struct qbman_result *get_swp_active_dqs(uint16_t dpio_index)
 	return rte_global_active_dqs_list[dpio_index].global_active_dqs;
 }
 
+/* 00 00 00 - last 6 bit represent data, annotation,
+ * context stashing setting 01 01 00 (0x14)
+ * (in following order ->DS AS CS)
+ * to enable 1 line data, 1 line annotation.
+ * For LX2, this setting should be 01 00 00 (0x10)
+ */
+#define DPAA2_FLC_STASHING_MAX_BIT_SIZE 2
+#define DPAA2_FLC_STASHING_MAX_CACHE_LINE \
+	((1ULL << DPAA2_FLC_STASHING_MAX_BIT_SIZE) - 1)
+
+enum dpaa2_flc_stashing_type {
+	DPAA2_FLC_CNTX_STASHING = 0,
+	DPAA2_FLC_ANNO_STASHING =
+		DPAA2_FLC_CNTX_STASHING + DPAA2_FLC_STASHING_MAX_BIT_SIZE,
+	DPAA2_FLC_DATA_STASHING =
+		DPAA2_FLC_ANNO_STASHING + DPAA2_FLC_STASHING_MAX_BIT_SIZE,
+	DPAA2_FLC_END_STASHING =
+		DPAA2_FLC_DATA_STASHING + DPAA2_FLC_STASHING_MAX_BIT_SIZE
+};
+
+#define DPAA2_STASHING_ALIGN_SIZE (1 << DPAA2_FLC_END_STASHING)
+
+static inline void
+dpaa2_flc_stashing_set(enum dpaa2_flc_stashing_type type,
+	uint8_t cache_line, uint64_t *flc)
+{
+	RTE_ASSERT(cache_line <= DPAA2_FLC_STASHING_MAX_CACHE_LINE);
+	RTE_ASSERT(type == DPAA2_FLC_CNTX_STASHING ||
+		type == DPAA2_FLC_ANNO_STASHING ||
+		type == DPAA2_FLC_DATA_STASHING);
+
+	(*flc) &= ~(DPAA2_FLC_STASHING_MAX_CACHE_LINE << type);
+	(*flc) |= (cache_line << type);
+}
+
+static inline void
+dpaa2_flc_stashing_clear_all(uint64_t *flc)
+{
+	dpaa2_flc_stashing_set(DPAA2_FLC_CNTX_STASHING, 0, flc);
+	dpaa2_flc_stashing_set(DPAA2_FLC_ANNO_STASHING, 0, flc);
+	dpaa2_flc_stashing_set(DPAA2_FLC_DATA_STASHING, 0, flc);
+}
+
 static inline
 void set_swp_active_dqs(uint16_t dpio_index, struct qbman_result *dqs)
 {
diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c
index 449bbda7ca..726bc0cf3e 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.c
+++ b/drivers/net/dpaa2/dpaa2_ethdev.c
@@ -786,17 +786,20 @@ dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
 	if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
 		options |= DPNI_QUEUE_OPT_FLC;
 		cfg.flc.stash_control = true;
-		cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
-		/* 00 00 00 - last 6 bit represent annotation, context stashing,
-		 * data stashing setting 01 01 00 (0x14)
-		 * (in following order ->DS AS CS)
-		 * to enable 1 line data, 1 line annotation.
-		 * For LX2, this setting should be 01 00 00 (0x10)
-		 */
-		if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
-			cfg.flc.value |= 0x10;
-		else
-			cfg.flc.value |= 0x14;
+		dpaa2_flc_stashing_clear_all(&cfg.flc.value);
+		if (getenv("DPAA2_DATA_STASHING_OFF")) {
+			dpaa2_flc_stashing_set(DPAA2_FLC_DATA_STASHING, 0,
+				&cfg.flc.value);
+			dpaa2_q->data_stashing_off = 1;
+		} else {
+			dpaa2_flc_stashing_set(DPAA2_FLC_DATA_STASHING, 1,
+				&cfg.flc.value);
+			dpaa2_q->data_stashing_off = 0;
+		}
+		if ((dpaa2_svr_family & 0xffff0000) != SVR_LX2160A) {
+			dpaa2_flc_stashing_set(DPAA2_FLC_ANNO_STASHING, 1,
+				&cfg.flc.value);
+		}
 	}
 	ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
 			     dpaa2_q->tc_index, flow_id, options, &cfg);
-- 
2.25.1

[v2 4/7] crypto/dpaa2_sec: enhance IPsec RFLC handling

[Gagandeep Singh]

From: Jun Yang <jun.yang@nxp.com>

Point Response FLC to FLC(SEC descriptor context).
Response FLC can be used for debug purpose in dequeue process.
Enable data stashing only. Annotation stashing is disabled which
is not suitable for SEC and impacts performance.

Signed-off-by: Jun Yang <jun.yang@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
 drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 44 ++++++++++++---------
 1 file changed, 26 insertions(+), 18 deletions(-)

diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
index e0b8bacdb8..0e30192b30 100644
--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
@@ -2005,7 +2005,7 @@ dpaa2_sec_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
 	struct fsl_mc_io *dpseci = (struct fsl_mc_io *)priv->hw;
 	struct dpseci_rx_queue_cfg cfg;
 	int32_t retcode;
-	char str[30];
+	char str[RTE_MEMZONE_NAMESIZE];
 
 	PMD_INIT_FUNC_TRACE();
 
@@ -2065,8 +2065,7 @@ dpaa2_sec_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
 		return -ENOMEM;
 	}
 
-	cfg.options = cfg.options | DPSECI_QUEUE_OPT_USER_CTX;
-	cfg.user_ctx = (size_t)(&qp->rx_vq);
+	cfg.dest_cfg.dest_type = DPSECI_DEST_NONE;
 	retcode = dpseci_set_rx_queue(dpseci, CMD_PRI_LOW, priv->token,
 				      qp_id, &cfg);
 	return retcode;
@@ -3060,14 +3059,19 @@ dpaa2_sec_set_ipsec_session(struct rte_cryptodev *dev,
 	struct alginfo authdata, cipherdata;
 	int bufsize;
 	struct sec_flow_context *flc;
+	uint64_t flc_iova;
 	int ret = -1;
 
 	PMD_INIT_FUNC_TRACE();
 
-	priv = (struct ctxt_priv *)rte_zmalloc(NULL,
-				sizeof(struct ctxt_priv) +
-				sizeof(struct sec_flc_desc),
-				RTE_CACHE_LINE_SIZE);
+	RTE_SET_USED(dev);
+
+	/** Make FLC address to align with stashing, low 6 bits are used
+	 * control stashing.
+	 */
+	priv = rte_zmalloc(NULL, sizeof(struct ctxt_priv) +
+		sizeof(struct sec_flc_desc),
+		DPAA2_STASHING_ALIGN_SIZE);
 
 	if (priv == NULL) {
 		DPAA2_SEC_ERR("No memory for priv CTXT");
@@ -3077,10 +3081,12 @@ dpaa2_sec_set_ipsec_session(struct rte_cryptodev *dev,
 	flc = &priv->flc_desc[0].flc;
 
 	if (ipsec_xform->life.bytes_hard_limit != 0 ||
-	    ipsec_xform->life.bytes_soft_limit != 0 ||
-	    ipsec_xform->life.packets_hard_limit != 0 ||
-	    ipsec_xform->life.packets_soft_limit != 0)
+		ipsec_xform->life.bytes_soft_limit != 0 ||
+		ipsec_xform->life.packets_hard_limit != 0 ||
+		ipsec_xform->life.packets_soft_limit != 0) {
+		rte_free(priv);
 		return -ENOTSUP;
+	}
 
 	memset(session, 0, sizeof(dpaa2_sec_session));
 
@@ -3330,24 +3336,26 @@ dpaa2_sec_set_ipsec_session(struct rte_cryptodev *dev,
 				1, 0, (rta_sec_era >= RTA_SEC_ERA_10) ?
 				SHR_WAIT : SHR_SERIAL,
 				&decap_pdb, &cipherdata, &authdata);
-	} else
+	} else {
+		ret = -EINVAL;
 		goto out;
+	}
 
 	if (bufsize < 0) {
+		ret = -EINVAL;
 		DPAA2_SEC_ERR("Crypto: Invalid SEC-DESC buffer length");
 		goto out;
 	}
 
 	flc->word1_sdl = (uint8_t)bufsize;
 
-	/* Enable the stashing control bit */
+	flc_iova = DPAA2_VADDR_TO_IOVA(flc);
+	/* Enable the stashing control bit and data stashing only.*/
 	DPAA2_SET_FLC_RSC(flc);
-	flc->word2_rflc_31_0 = lower_32_bits(
-			(size_t)&(((struct dpaa2_sec_qp *)
-			dev->data->queue_pairs[0])->rx_vq) | 0x14);
-	flc->word3_rflc_63_32 = upper_32_bits(
-			(size_t)&(((struct dpaa2_sec_qp *)
-			dev->data->queue_pairs[0])->rx_vq));
+	dpaa2_flc_stashing_set(DPAA2_FLC_DATA_STASHING, 1,
+		&flc_iova);
+	flc->word2_rflc_31_0 = lower_32_bits(flc_iova);
+	flc->word3_rflc_63_32 = upper_32_bits(flc_iova);
 
 	/* Set EWS bit i.e. enable write-safe */
 	DPAA2_SET_FLC_EWS(flc);
-- 
2.25.1

[v2 5/7] crypto/dpaa2_sec: enhance pdcp FLC handling

[Gagandeep Singh]

From: Jun Yang <jun.yang@nxp.com>

Set RFLC with FLC IOVA address and data stashing only.

Signed-off-by: Jun Yang <jun.yang@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
 drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
index 0e30192b30..ff24a8919a 100644
--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
@@ -3389,6 +3389,7 @@ dpaa2_sec_set_pdcp_session(struct rte_cryptodev *dev,
 	struct alginfo *p_authdata = NULL;
 	int bufsize = -1;
 	struct sec_flow_context *flc;
+	uint64_t flc_iova;
 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
 	int swap = true;
 #else
@@ -3397,6 +3398,8 @@ dpaa2_sec_set_pdcp_session(struct rte_cryptodev *dev,
 
 	PMD_INIT_FUNC_TRACE();
 
+	RTE_SET_USED(dev);
+
 	memset(session, 0, sizeof(dpaa2_sec_session));
 
 	priv = (struct ctxt_priv *)rte_zmalloc(NULL,
@@ -3646,14 +3649,13 @@ dpaa2_sec_set_pdcp_session(struct rte_cryptodev *dev,
 		goto out;
 	}
 
-	/* Enable the stashing control bit */
+	flc_iova = DPAA2_VADDR_TO_IOVA(flc);
+	/* Enable the stashing control bit and data stashing only.*/
 	DPAA2_SET_FLC_RSC(flc);
-	flc->word2_rflc_31_0 = lower_32_bits(
-			(size_t)&(((struct dpaa2_sec_qp *)
-			dev->data->queue_pairs[0])->rx_vq) | 0x14);
-	flc->word3_rflc_63_32 = upper_32_bits(
-			(size_t)&(((struct dpaa2_sec_qp *)
-			dev->data->queue_pairs[0])->rx_vq));
+	dpaa2_flc_stashing_set(DPAA2_FLC_DATA_STASHING, 1,
+		&flc_iova);
+	flc->word2_rflc_31_0 = lower_32_bits(flc_iova);
+	flc->word3_rflc_63_32 = upper_32_bits(flc_iova);
 
 	flc->word1_sdl = (uint8_t)bufsize;
 
-- 
2.25.1

[v2 6/7] crypto/dpaa2_sec: remove prefetch code in event mode

[Gagandeep Singh]

From: Jun Yang <jun.yang@nxp.com>

Should not prefetch mbuf and crypto_op which are not touched
by hardware.

Signed-off-by: Jun Yang <jun.yang@nxp.com>
---
 drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 20 +-------------------
 1 file changed, 1 insertion(+), 19 deletions(-)

diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
index ff24a8919a..1e28c71b53 100644
--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
@@ -3991,12 +3991,6 @@ dpaa2_sec_process_parallel_event(struct qbman_swp *swp,
 				 struct rte_event *ev)
 {
 	struct dpaa2_sec_qp *qp;
-	/* Prefetching mbuf */
-	rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd)-
-		rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size));
-
-	/* Prefetching ipsec crypto_op stored in priv data of mbuf */
-	rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd)-64));
 
 	qp = container_of(rxq, struct dpaa2_sec_qp, rx_vq);
 	ev->flow_id = rxq->ev.flow_id;
@@ -4010,6 +4004,7 @@ dpaa2_sec_process_parallel_event(struct qbman_swp *swp,
 
 	qbman_swp_dqrr_consume(swp, dq);
 }
+
 static void
 dpaa2_sec_process_atomic_event(struct qbman_swp *swp __rte_unused,
 				 const struct qbman_fd *fd,
@@ -4020,12 +4015,6 @@ dpaa2_sec_process_atomic_event(struct qbman_swp *swp __rte_unused,
 	uint8_t dqrr_index;
 	struct dpaa2_sec_qp *qp;
 	struct rte_crypto_op *crypto_op;
-	/* Prefetching mbuf */
-	rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd)-
-		rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size));
-
-	/* Prefetching ipsec crypto_op stored in priv data of mbuf */
-	rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd)-64));
 
 	qp = container_of(rxq, struct dpaa2_sec_qp, rx_vq);
 	ev->flow_id = rxq->ev.flow_id;
@@ -4055,13 +4044,6 @@ dpaa2_sec_process_ordered_event(struct qbman_swp *swp,
 	struct rte_crypto_op *crypto_op;
 	struct dpaa2_sec_qp *qp;
 
-	/* Prefetching mbuf */
-	rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd)-
-		rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size));
-
-	/* Prefetching ipsec crypto_op stored in priv data of mbuf */
-	rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd)-64));
-
 	qp = container_of(rxq, struct dpaa2_sec_qp, rx_vq);
 	ev->flow_id = rxq->ev.flow_id;
 	ev->sub_event_type = rxq->ev.sub_event_type;
-- 
2.25.1

[v2 7/7] crypto/dpaa2_sec: rework debug code

[Gagandeep Singh]

From: Jun Yang <jun.yang@nxp.com>

Output debug information according to various modes.

Signed-off-by: Jun Yang <jun.yang@nxp.com>
---
 drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 87 +++++++++++++++------
 1 file changed, 63 insertions(+), 24 deletions(-)

diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
index 1e28c71b53..a293a21881 100644
--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
@@ -1095,7 +1095,7 @@ build_auth_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
 
 static int
 build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
-		struct qbman_fd *fd, __rte_unused uint16_t bpid)
+		struct qbman_fd *fd, uint16_t bpid)
 {
 	struct rte_crypto_sym_op *sym_op = op->sym;
 	struct qbman_fle *ip_fle, *op_fle, *sge, *fle;
@@ -1105,6 +1105,10 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
 	struct rte_mbuf *mbuf;
 	uint8_t *iv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,
 			sess->iv.offset);
+#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
+	char debug_str[1024];
+	int offset;
+#endif
 
 	data_len = sym_op->cipher.data.length;
 	data_offset = sym_op->cipher.data.offset;
@@ -1210,14 +1214,26 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
 	DPAA2_SET_FD_COMPOUND_FMT(fd);
 	DPAA2_SET_FD_FLC(fd, DPAA2_VADDR_TO_IOVA(flc));
 
-	DPAA2_SEC_DP_DEBUG(
-		"CIPHER SG: fdaddr =%" PRIx64 " bpid =%d meta =%d"
-		" off =%d, len =%d\n",
+#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
+	offset = sprintf(debug_str,
+		"CIPHER SG: fdaddr =%" PRIx64 ", from %s pool ",
 		DPAA2_GET_FD_ADDR(fd),
-		DPAA2_GET_FD_BPID(fd),
-		rte_dpaa2_bpid_info[bpid].meta_data_size,
-		DPAA2_GET_FD_OFFSET(fd),
-		DPAA2_GET_FD_LEN(fd));
+		bpid < MAX_BPID ? "SW" : "BMAN");
+	if (bpid < MAX_BPID) {
+		offset += sprintf(&debug_str[offset],
+			"bpid = %d ", bpid);
+	}
+	offset += sprintf(&debug_str[offset],
+		"private size = %d ",
+		mbuf->pool->private_data_size);
+	offset += sprintf(&debug_str[offset],
+		"off =%d, len =%d\n",
+		DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_LEN(fd));
+		DPAA2_SEC_DP_DEBUG("%s", debug_str);
+#else
+	RTE_SET_USED(bpid);
+#endif
+
 	return 0;
 }
 
@@ -1233,6 +1249,10 @@ build_cipher_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
 	uint8_t *iv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,
 			sess->iv.offset);
 	struct rte_mbuf *dst;
+#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
+	char debug_str[1024];
+	int offset;
+#endif
 
 	data_len = sym_op->cipher.data.length;
 	data_offset = sym_op->cipher.data.offset;
@@ -1324,14 +1344,23 @@ build_cipher_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
 	DPAA2_SET_FLE_FIN(sge);
 	DPAA2_SET_FLE_FIN(fle);
 
-	DPAA2_SEC_DP_DEBUG(
-		"CIPHER: fdaddr =%" PRIx64 " bpid =%d meta =%d"
-		" off =%d, len =%d\n",
+#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
+	offset = sprintf(debug_str,
+		"CIPHER: fdaddr =%" PRIx64 ", from %s pool ",
 		DPAA2_GET_FD_ADDR(fd),
-		DPAA2_GET_FD_BPID(fd),
-		rte_dpaa2_bpid_info[bpid].meta_data_size,
-		DPAA2_GET_FD_OFFSET(fd),
-		DPAA2_GET_FD_LEN(fd));
+		bpid < MAX_BPID ? "SW" : "BMAN");
+	if (bpid < MAX_BPID) {
+		offset += sprintf(&debug_str[offset],
+			"bpid = %d ", bpid);
+	}
+	offset += sprintf(&debug_str[offset],
+			"private size = %d ",
+			dst->pool->private_data_size);
+	offset += sprintf(&debug_str[offset],
+			"off =%d, len =%d\n",
+			DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_LEN(fd));
+	DPAA2_SEC_DP_DEBUG("%s", debug_str);
+#endif
 
 	return 0;
 }
@@ -1564,6 +1593,10 @@ sec_fd_to_mbuf(const struct qbman_fd *fd, struct dpaa2_sec_qp *qp)
 	struct qbman_fle *fle;
 	struct rte_crypto_op *op;
 	struct rte_mbuf *dst, *src;
+#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
+	char debug_str[1024];
+	int offset;
+#endif
 
 	if (DPAA2_FD_GET_FORMAT(fd) == qbman_fd_single)
 		return sec_simple_fd_to_mbuf(fd);
@@ -1602,15 +1635,21 @@ sec_fd_to_mbuf(const struct qbman_fd *fd, struct dpaa2_sec_qp *qp)
 		dst->data_len = len;
 	}
 
-	DPAA2_SEC_DP_DEBUG("mbuf %p BMAN buf addr %p,"
-		" fdaddr =%" PRIx64 " bpid =%d meta =%d off =%d, len =%d\n",
-		(void *)dst,
-		dst->buf_addr,
-		DPAA2_GET_FD_ADDR(fd),
-		DPAA2_GET_FD_BPID(fd),
-		rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
-		DPAA2_GET_FD_OFFSET(fd),
-		DPAA2_GET_FD_LEN(fd));
+#if (RTE_LOG_DEBUG <= RTE_LOG_DP_LEVEL)
+	offset = sprintf(debug_str, "Mbuf %p from %s pool ",
+			dst, DPAA2_GET_FD_IVP(fd) ? "SW" : "BMAN");
+	if (!DPAA2_GET_FD_IVP(fd)) {
+		offset += sprintf(&debug_str[offset], "bpid = %d ",
+				DPAA2_GET_FD_BPID(fd));
+	}
+	offset += sprintf(&debug_str[offset],
+			"private size = %d ", dst->pool->private_data_size);
+	offset += sprintf(&debug_str[offset],
+			"addr %p, fdaddr =%" PRIx64 ", off =%d, len =%d\n",
+			dst->buf_addr, DPAA2_GET_FD_ADDR(fd),
+			DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_LEN(fd));
+	DPAA2_SEC_DP_DEBUG("%s", debug_str);
+#endif
 
 	/* free the fle memory */
 	if (likely(rte_pktmbuf_is_contiguous(src))) {
-- 
2.25.1

RE: [EXTERNAL] [v2 0/7] DPAA2 crypto changes

[Akhil Goyal]

> v2 changes:
> 	* fix patch sequence
> 	* add missing code in
> 	"crypto/dpaa2_sec: rework debug code"
> 
> Changes related to crypto driver
> 
> Gagandeep Singh (1):
>   crypto/dpaa2_sec: fix memory leak
> 
> Jun Yang (5):
>   net/dpaa2: support FLC stashing API
>   crypto/dpaa2_sec: enhance IPsec RFLC handling
>   crypto/dpaa2_sec: enhance pdcp FLC handling
>   crypto/dpaa2_sec: remove prefetch code in event mode
>   crypto/dpaa2_sec: rework debug code
> 
> Varun Sethi (1):
>   common/dpaax: caamflib: fix PDCP SNOW-ZUC wdog DECO err
> 
>  drivers/bus/fslmc/portal/dpaa2_hw_pvt.h     |  44 +++++
>  drivers/common/dpaax/caamflib/desc/pdcp.h   |  10 ++
>  drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 168 ++++++++++++--------
>  drivers/net/dpaa2/dpaa2_ethdev.c            |  25 +--
>  4 files changed, 168 insertions(+), 79 deletions(-)

Series applied to dpdk-next-crypto
Thanks.