From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8D281A0A02; Tue, 18 May 2021 14:41:16 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 10D444068E; Tue, 18 May 2021 14:41:16 +0200 (CEST) Received: from szxga07-in.huawei.com (szxga07-in.huawei.com [45.249.212.35]) by mails.dpdk.org (Postfix) with ESMTP id C34A440041 for ; Tue, 18 May 2021 14:41:13 +0200 (CEST) Received: from dggems704-chm.china.huawei.com (unknown [172.30.72.59]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4FkwXF3BPszCv17; Tue, 18 May 2021 20:38:21 +0800 (CST) Received: from dggpeml500024.china.huawei.com (7.185.36.10) by dggems704-chm.china.huawei.com (10.3.19.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Tue, 18 May 2021 20:41:07 +0800 Received: from [127.0.0.1] (10.40.190.165) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Tue, 18 May 2021 20:41:06 +0800 To: "thomas@monjalon.net" , "ferruh.yigit@intel.com" CC: Honnappa Nagarahalli , "dev@dpdk.org" , "jerinj@marvell.com" , Ruifeng Wang , "viktorin@rehivetech.com" , "bruce.richardson@intel.com" , "jerinjacobk@gmail.com" , "juraj.linkes@pantheon.tech" , nd References: <1620808126-18876-1-git-send-email-fengchengwen@huawei.com> <1620986039-29475-1-git-send-email-fengchengwen@huawei.com> <1620986039-29475-3-git-send-email-fengchengwen@huawei.com> From: fengchengwen Message-ID: Date: Tue, 18 May 2021 20:41:06 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.40.190.165] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To dggpeml500024.china.huawei.com (7.185.36.10) X-CFilter-Loop: Reflected Subject: Re: [dpdk-dev] [PATCH v5 2/2] net/hns3: refactor SVE code compile method X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi, Thomas, Ferruh This patch is part of the hns3 SVE compilation solution and can work independently. Could you review it ? Best regards On 2021/5/14 22:12, Honnappa Nagarahalli wrote: > > >> >> Currently, the SVE code is compiled only when -march supports SVE (e.g. '- >> march=armv8.2a+sve'), there maybe some problem[1] with this approach. >> >> The solution: >> a. If the minimum instruction set support SVE then compiles it. >> b. Else if the compiler support SVE then compiles it. >> c. Otherwise don't compile it. >> >> [1] https://mails.dpdk.org/archives/dev/2021-April/208189.html >> >> Fixes: 8c25b02b082a ("net/hns3: fix enabling SVE Rx/Tx") >> Fixes: 952ebacce4f2 ("net/hns3: support SVE Rx") >> Cc: stable@dpdk.org >> >> Signed-off-by: Chengwen Feng > Looks good to me. > Reviewed-by: Honnappa Nagarahalli > >> --- >> drivers/net/hns3/hns3_rxtx.c | 2 +- >> drivers/net/hns3/meson.build | 13 +++++++++++++ >> 2 files changed, 14 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c >> index 1d7a769..4ef20c6 100644 >> --- a/drivers/net/hns3/hns3_rxtx.c >> +++ b/drivers/net/hns3/hns3_rxtx.c >> @@ -2808,7 +2808,7 @@ hns3_get_default_vec_support(void) >> static bool >> hns3_get_sve_support(void) >> { >> -#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_SVE) >> +#if defined(CC_SVE_SUPPORT) >> if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_256) >> return false; >> if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE)) >> diff --git a/drivers/net/hns3/meson.build b/drivers/net/hns3/meson.build >> index 53c7df7..8563d70 100644 >> --- a/drivers/net/hns3/meson.build >> +++ b/drivers/net/hns3/meson.build >> @@ -35,7 +35,20 @@ deps += ['hash'] >> >> if arch_subdir == 'arm' and dpdk_conf.get('RTE_ARCH_64') >> sources += files('hns3_rxtx_vec.c') >> + >> + # compile SVE when: >> + # a. support SVE in minimum instruction set baseline >> + # b. it's not minimum instruction set, but compiler support >> if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' >> + cflags += ['-DCC_SVE_SUPPORT'] >> sources += files('hns3_rxtx_vec_sve.c') >> + elif cc.has_argument('-march=armv8.2-a+sve') >> + cflags += ['-DCC_SVE_SUPPORT'] >> + hns3_sve_lib = static_library('hns3_sve_lib', >> + 'hns3_rxtx_vec_sve.c', >> + dependencies: [static_rte_ethdev], >> + include_directories: includes, >> + c_args: [cflags, '-march=armv8.2-a+sve']) >> + objs += hns3_sve_lib.extract_objects('hns3_rxtx_vec_sve.c') >> endif >> endif >> -- >> 2.8.1 > > > . >