From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id D2C675F36 for ; Tue, 20 Mar 2018 10:47:48 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Mar 2018 02:47:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,334,1517904000"; d="scan'208";a="209746000" Received: from unknown (HELO [10.237.220.112]) ([10.237.220.112]) by orsmga005.jf.intel.com with ESMTP; 20 Mar 2018 02:47:43 -0700 To: Olivier Matz Cc: dev@dpdk.org, Thomas Monjalon , Yuanhan Liu , Maxime Coquelin , Tiwei Bie , keith.wiles@intel.com, jianfeng.tan@intel.com, andras.kovacs@ericsson.com, laszlo.vadkeri@ericsson.com, benjamin.walker@intel.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, kuralamudhan.ramakrishnan@intel.com, louise.m.daly@intel.com, nelio.laranjeiro@6wind.com, yskoh@mellanox.com, pepperjo@japf.ch, jerin.jacob@caviumnetworks.com, hemant.agrawal@nxp.com References: <18f4ee0ba172f3bb80608694eb283cd496930675.1520083504.git.anatoly.burakov@intel.com> <20180319173904.u3f67wmlact2xwh6@platinum> From: "Burakov, Anatoly" Message-ID: Date: Tue, 20 Mar 2018 09:47:43 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <20180319173904.u3f67wmlact2xwh6@platinum> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Subject: Re: [dpdk-dev] [PATCH 13/41] eal: replace memseg with memseg lists X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 20 Mar 2018 09:47:49 -0000 On 19-Mar-18 5:39 PM, Olivier Matz wrote: > On Sat, Mar 03, 2018 at 01:46:01PM +0000, Anatoly Burakov wrote: > > [...] > >> --- a/config/common_base >> +++ b/config/common_base >> @@ -61,7 +61,20 @@ CONFIG_RTE_CACHE_LINE_SIZE=64 >> CONFIG_RTE_LIBRTE_EAL=y >> CONFIG_RTE_MAX_LCORE=128 >> CONFIG_RTE_MAX_NUMA_NODES=8 >> -CONFIG_RTE_MAX_MEMSEG=256 >> +CONFIG_RTE_MAX_MEMSEG_LISTS=32 >> +# each memseg list will be limited to either RTE_MAX_MEMSEG_PER_LIST pages >> +# or RTE_MAX_MEM_PER_LIST gigabytes worth of memory, whichever is the smallest >> +CONFIG_RTE_MAX_MEMSEG_PER_LIST=8192 >> +CONFIG_RTE_MAX_MEM_PER_LIST=32 >> +# a "type" is a combination of page size and NUMA node. total number of memseg >> +# lists per type will be limited to either RTE_MAX_MEMSEG_PER_TYPE pages (split >> +# over multiple lists of RTE_MAX_MEMSEG_PER_LIST pages), or RTE_MAX_MEM_PER_TYPE >> +# gigabytes of memory (split over multiple lists of RTE_MAX_MEM_PER_LIST), >> +# whichever is the smallest >> +CONFIG_RTE_MAX_MEMSEG_PER_TYPE=32768 >> +CONFIG_RTE_MAX_MEM_PER_TYPE=128 >> +# legacy mem mode only >> +CONFIG_RTE_MAX_LEGACY_MEMSEG=256 > > Would it be possible to suffix CONFIG_RTE_MAX_MEM_PER_LIST and > CONFIG_RTE_MAX_MEM_PER_TYPE with _GB? It's not that obvious that is it > gigabytes. Sure, will add this. > > What is the impact of changing one of these values on the ABI? Some of them will change the ABI, some won't. MAX_MEMSEG_LISTS will change the ABI because it's in the rte_eal_memconfig, but other values are not and are only used during init (and LEGACY_MEMSEG is already removed in GitHub code). > And what would be the impact on performance? Depending on what you mean by performance. Generally, no impact on performance will be noticeable because we're not really doing anything differently - a page is a page, no matter how or when it is mapped. These changes might also speed up some lookup operations on memseg lists themselves. > The underlying question is: shall we increase these values to avoid changing them later? > I do plan to increase the MAX_MEMSEG_LISTS value to at least 64. -- Thanks, Anatoly