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Thu, 8 Sep 2022 18:44:09 +0000 (GMT) Received: from [9.211.79.90] (unknown [9.211.79.90]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTP; Thu, 8 Sep 2022 18:44:09 +0000 (GMT) Message-ID: Date: Thu, 8 Sep 2022 11:33:04 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 Subject: Re: [PATCH v2 1/5] examples/l3fwd: fix port group mask generation Content-Language: en-US To: pbhagavatula@marvell.com, jerinj@marvell.com Cc: dev@dpdk.org, stable@dpdk.org References: <20220829094442.3422-1-pbhagavatula@marvell.com> <20220902091833.9074-1-pbhagavatula@marvell.com> From: David Christensen In-Reply-To: <20220902091833.9074-1-pbhagavatula@marvell.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: n0sO9izY9j4GtZa5jqFnisL8P3SRBrML X-Proofpoint-ORIG-GUID: n0sO9izY9j4GtZa5jqFnisL8P3SRBrML X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-08_10,2022-09-08_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 clxscore=1011 malwarescore=0 priorityscore=1501 phishscore=0 mlxlogscore=999 adultscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2209080065 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On 9/2/22 2:18 AM, pbhagavatula@marvell.com wrote: > From: Pavan Nikhilesh > > Fix port group mask generation in altivec, vec_any_eq returns > 0 or 1 while port_groupx4 expects comparison mask result. > > Fixes: 2193b7467f7a ("examples/l3fwd: optimize packet processing on powerpc") > Cc: stable@dpdk.org > > Signed-off-by: Pavan Nikhilesh > --- > v2 Changes: > - Fix PPC, RISC-V, aarch32 compilation. > > examples/common/altivec/port_group.h | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > diff --git a/examples/common/altivec/port_group.h b/examples/common/altivec/port_group.h > index 5e209b02fa..592ef80b7f 100644 > --- a/examples/common/altivec/port_group.h > +++ b/examples/common/altivec/port_group.h > @@ -26,12 +26,19 @@ port_groupx4(uint16_t pn[FWDSTEP + 1], uint16_t *lp, > uint16_t u16[FWDSTEP + 1]; > uint64_t u64; > } *pnum = (void *)pn; > + union u_vec { > + __vector unsigned short v_us; > + unsigned short s[8]; > + }; > > + union u_vec res; > int32_t v; > > - v = vec_any_eq(dp1, dp2); > - > + dp1 = (__vector unsigned short)vec_cmpeq(dp1, dp2); Altivec vec_cmpeq() is similar to Intel _mm_cmpeq_*(), so this looks right to me. > + res.v_us = dp1; > > + v = (res.s[0] & 0x1) | (res.s[1] & 0x2) | (res.s[2] & 0x4) | > + (res.s[3] & 0x8); This can be vectorized too. The Intel _mm_unpacklo_epi16() intrinsic can be replaced with the following Altivec code: extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_unpacklo_epi16 (__m128i __A, __m128i __B) { return (__m128i) vec_mergeh ((__v8hi)__A, (__v8hi)__B); } The Intel _mm_movemask_ps() intrinsic can be replaced with the following Altivec implementation: /* Creates a 4-bit mask from the most significant bits of the SPFP values. */ extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_movemask_ps (__m128 __A) { __vector unsigned long long result; static const __vector unsigned int perm_mask = { #ifdef __LITTLE_ENDIAN__ 0x00204060, 0x80808080, 0x80808080, 0x80808080 #else 0x80808080, 0x80808080, 0x80808080, 0x00204060 #endif }; result = ((__vector unsigned long long) vec_vbpermq ((__vector unsigned char) __A, (__vector unsigned char) perm_mask)); #ifdef __LITTLE_ENDIAN__ return result[1]; #else return result[0]; #endif } Dave