From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BD78045501; Wed, 26 Jun 2024 14:05:48 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CA083433FD; Wed, 26 Jun 2024 13:57:18 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by mails.dpdk.org (Postfix) with ESMTP id 3A53D42E95 for ; Wed, 26 Jun 2024 13:45:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719402334; x=1750938334; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Cp4YCd1cC18t6wDZj4h9TwDvraPVDnwSWbHof6/9N/0=; b=oKJpPl9osOVgnA9xd9LCafiLTggBuK03FOdpLJ6l1hKz3wH3Yr0w+rK5 xtPm+2V7RR/EbrwVym5Izd8m3wfD1dHMNah0kLy+4LwB+pbYy87L+HeF6 gH8TJMFmiBBhp3IqHJHW5g6iCd2u4VML3TswVL1md2IP4NJR4OerO/Mp+ vAMcA8YHSJtnpoq9AJub6qdv8TR8xEeLhYfLU9S+uWEsQlc2meg18XZTs AF0sNLjprm+QbVakVIRqbkjOgGtXL1f5lRmFehdeiPEpx+aH9W6m0KVQb mmT1mYiyDCNcpKm0agiIEvuzFi7uAyCyj0ZicQk4Iroyiw0nP2Pohx7oJ Q==; X-CSE-ConnectionGUID: +W0TyinaTimgVd0w5yoG4Q== X-CSE-MsgGUID: 7G/EJ4xoQb6OoSdmjHZxvw== X-IronPort-AV: E=McAfee;i="6700,10204,11114"; a="38979578" X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="38979578" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jun 2024 04:45:33 -0700 X-CSE-ConnectionGUID: PpP8NoegQVS7sJ5p75mu8A== X-CSE-MsgGUID: s53Y0nDBRheHi0F1t9ulng== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="43874481" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa010.jf.intel.com with ESMTP; 26 Jun 2024 04:45:33 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Karol Kolacinski , ian.stokes@intel.com, bruce.richardson@intel.com Subject: [PATCH v4 090/103] net/ice/base: cleanup timestamp registers correctly Date: Wed, 26 Jun 2024 12:42:18 +0100 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Karol Kolacinski E822 PHY TS registers should not be written and the only way to cleanup them is to reset QUAD memory. To ensure that the status bit for the timestamp index is cleared, ensure that ice_clear_phy_tstamp implementations first read the timestamp out. Implementations which can write the register continue to do so. Add a note to indicate this function should only be called on timestamps which have their valid bit set. Signed-off-by: Karol Kolacinski Signed-off-by: Jacob Keller Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_ptp_hw.c | 46 ++++++++++++++++++------------- 1 file changed, 27 insertions(+), 19 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index bf3c32ae64..bba228ed39 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -1540,8 +1540,18 @@ static int ice_clear_phy_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx) { int err; + u64 unused_tstamp; u16 lo_addr; + /* Read the timestamp register to ensure the timestamp status bit is + * cleared. + */ + err = ice_read_phy_tstamp_eth56g(hw, port, idx, &unused_tstamp); + if (err) { + ice_debug(hw, ICE_DBG_PTP, "Failed to read the PHY timestamp register for port %u, idx %u, err %d\n", + port, idx, err); + } + lo_addr = (u16)PHY_TSTAMP_L(idx); err = ice_phy_port_mem_write_eth56g(hw, port, lo_addr, 0); @@ -2997,23 +3007,13 @@ ice_read_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp) static int ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx) { + u64 unused_tstamp; int err; - u16 lo_addr, hi_addr; - lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx); - hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx); - - err = ice_write_quad_reg_e822(hw, quad, lo_addr, 0); - if (err) { - ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, err %d\n", - err); - return err; - } - - err = ice_write_quad_reg_e822(hw, quad, hi_addr, 0); + err = ice_read_phy_tstamp_e822(hw, quad, idx, &unused_tstamp); if (err) { - ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, err %d\n", - err); + ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for quad %u, idx %u, err %d\n", + quad, idx, err); return err; } @@ -4939,23 +4939,31 @@ ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) static int ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx) { - int err; u32 lo_addr, hi_addr; + u64 unused_tstamp; + int err; + + err = ice_read_phy_tstamp_e810(hw, lport, idx, &unused_tstamp); + if (err) { + ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for lport %u, idx %u, err %d\n", + lport, idx, err); + return err; + } lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); err = ice_write_phy_reg_e810(hw, lo_addr, 0); if (err) { - ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, err %d\n", - err); + ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for lport %u, idx %u, err %d\n", + lport, idx, err); return err; } err = ice_write_phy_reg_e810(hw, hi_addr, 0); if (err) { - ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, err %d\n", - err); + ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register for lport %u, idx %u, err %d\n", + lport, idx, err); return err; } -- 2.43.0