From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 51761A04B6; Mon, 12 Oct 2020 05:30:31 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8320B1D551; Mon, 12 Oct 2020 05:30:29 +0200 (CEST) Received: from incedge.chinasoftinc.com (unknown [114.113.233.8]) by dpdk.org (Postfix) with ESMTP id A57EC1BCC4 for ; Mon, 12 Oct 2020 05:30:26 +0200 (CEST) X-ASG-Debug-ID: 1602473424-149d114cae1317e0001-TfluYd Received: from mail.chinasoftinc.com (inccas001.ito.icss [10.168.0.51]) by incedge.chinasoftinc.com with ESMTP id HAlDHvnMQiVGe873 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 12 Oct 2020 11:30:24 +0800 (CST) X-Barracuda-Envelope-From: huwei013@chinasoftinc.com X-Barracuda-RBL-Trusted-Forwarder: 10.168.0.51 X-ASG-Whitelist: Client Received: from [192.168.1.199] (139.159.243.11) by INCCAS001.ito.icss (10.168.0.60) with Microsoft SMTP Server id 14.3.487.0; Mon, 12 Oct 2020 11:30:23 +0800 X-Barracuda-RBL-Trusted-Forwarder: 192.168.1.199 From: "Wei Hu (Xavier)" X-ASG-Orig-Subj: Re: [dpdk-dev] [PATCH v6 1/2] eal/arm64: update CPU flags To: Thomas Monjalon CC: , , , , , , Ferruh Yigit References: <20200817124703.58157-1-huwei013@chinasoftinc.com> <20200819105638.52010-1-huwei013@chinasoftinc.com> <20200819105638.52010-2-huwei013@chinasoftinc.com> Message-ID: Date: Mon, 12 Oct 2020 11:30:22 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <20200819105638.52010-2-huwei013@chinasoftinc.com> Content-Language: en-US X-Originating-IP: [139.159.243.11] X-Barracuda-Connect: inccas001.ito.icss[10.168.0.51] X-Barracuda-Start-Time: 1602473424 X-Barracuda-Encrypted: ECDHE-RSA-AES256-SHA X-Barracuda-URL: https://incspam.chinasofti.com:443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at chinasoftinc.com X-Barracuda-Scan-Msg-Size: 6951 Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 8bit X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Subject: Re: [dpdk-dev] [PATCH v6 1/2] eal/arm64: update CPU flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi, Thomas Monjalon For this series, ARM engineer has already given them backed by. If you have no other opinion, can we merge them? so we can continue to promote other patch sets accelerated by using SVE instructions. Hope for your reply, thanks.   Regards Xavier On 2020/8/19 18:56, Wei Hu (Xavier) wrote: > From: "Wei Hu (Xavier)" > > ARM64 Linux kernel updated the CPU flags using the HWCAP scheme. > The related marco definition can be found in linux kernel: > arch/arm64/include/uapi/asm/hwcap.h > > This patch incorporates those changes to the eal library. > > Signed-off-by: Chengwen Feng > Signed-off-by: Wei Hu (Xavier) > Reviewed-by: Ruifeng Wang > --- > v4 -> v5: > No change. > v3 -> v4: > Update commit log. > v2 -> v3: > 1. Change commit log. > 2. Add HWCAP2_FLAGM2 and HWCAP2_FRINT to rte_cpu_feature_table[]. > 3. Add the flags for newly added items into enum rte_cpu_flag_t. > v1 -> v2: > Adds more sve-related definition to rte_cpu_feature_table, > sunch as SVE2, etc. > --- > lib/librte_eal/arm/include/rte_cpuflags_64.h | 13 +++++++++++++ > lib/librte_eal/arm/rte_cpuflags.c | 13 +++++++++++++ > 2 files changed, 26 insertions(+) > > diff --git a/lib/librte_eal/arm/include/rte_cpuflags_64.h b/lib/librte_eal/arm/include/rte_cpuflags_64.h > index 95cc01474..aa7a56d49 100644 > --- a/lib/librte_eal/arm/include/rte_cpuflags_64.h > +++ b/lib/librte_eal/arm/include/rte_cpuflags_64.h > @@ -22,6 +22,19 @@ enum rte_cpu_flag_t { > RTE_CPUFLAG_SHA2, > RTE_CPUFLAG_CRC32, > RTE_CPUFLAG_ATOMICS, > + RTE_CPUFLAG_SVE, > + RTE_CPUFLAG_SVE2, > + RTE_CPUFLAG_SVEAES, > + RTE_CPUFLAG_SVEPMULL, > + RTE_CPUFLAG_SVEBITPERM, > + RTE_CPUFLAG_SVESHA3, > + RTE_CPUFLAG_SVESM4, > + RTE_CPUFLAG_FLAGM2, > + RTE_CPUFLAG_FRINT, > + RTE_CPUFLAG_SVEI8MM, > + RTE_CPUFLAG_SVEF32MM, > + RTE_CPUFLAG_SVEF64MM, > + RTE_CPUFLAG_SVEBF16, > RTE_CPUFLAG_AARCH64, > /* The last item */ > RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */ > diff --git a/lib/librte_eal/arm/rte_cpuflags.c b/lib/librte_eal/arm/rte_cpuflags.c > index caf3dc83a..7b257b787 100644 > --- a/lib/librte_eal/arm/rte_cpuflags.c > +++ b/lib/librte_eal/arm/rte_cpuflags.c > @@ -95,6 +95,19 @@ const struct feature_entry rte_cpu_feature_table[] = { > FEAT_DEF(SHA2, REG_HWCAP, 6) > FEAT_DEF(CRC32, REG_HWCAP, 7) > FEAT_DEF(ATOMICS, REG_HWCAP, 8) > + FEAT_DEF(SVE, REG_HWCAP, 22) > + FEAT_DEF(SVE2, REG_HWCAP2, 1) > + FEAT_DEF(SVEAES, REG_HWCAP2, 2) > + FEAT_DEF(SVEPMULL, REG_HWCAP2, 3) > + FEAT_DEF(SVEBITPERM, REG_HWCAP2, 4) > + FEAT_DEF(SVESHA3, REG_HWCAP2, 5) > + FEAT_DEF(SVESM4, REG_HWCAP2, 6) > + FEAT_DEF(FLAGM2, REG_HWCAP2, 7) > + FEAT_DEF(FRINT, REG_HWCAP2, 8) > + FEAT_DEF(SVEI8MM, REG_HWCAP2, 9) > + FEAT_DEF(SVEF32MM, REG_HWCAP2, 10) > + FEAT_DEF(SVEF64MM, REG_HWCAP2, 11) > + FEAT_DEF(SVEBF16, REG_HWCAP2, 12) > FEAT_DEF(AARCH64, REG_PLATFORM, 1) > }; > #endif /* RTE_ARCH */