From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C7681A034E; Wed, 9 Feb 2022 03:00:42 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6BBFB410F3; Wed, 9 Feb 2022 03:00:42 +0100 (CET) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id C04534067E for ; Wed, 9 Feb 2022 03:00:40 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644372040; x=1675908040; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=1MOd2QGFOAi1sYovJ9FTY1XSNxw6AvtzbDxFJKJvReQ=; b=QdosGRLGpgb1PY4bP4bgvsluYwLIwXMUuFzhz3GQthYt6kVApzmkQKKu 42jUDlYb9mU2Y1K9Xef3LWOL5aQV6j2ZMEJsuxjuNwFqWP9u2G7gLIOzy pJXkKqvXFQHbaZ+ODvUUmC64ESIT2igY2aMKF/7cbh5wuINodZjuXnMDp s3KbY2qnel+JKvbESACl6PwLyA3jOzTTd2rL0i7beRp7sNLbluxPWyrnj L9fvmskYeha4Xn4t0I+kalzvDzDXCu54K+0XIJA+PCIdmrqr2L85/wgmd BUwysOObr99i3cT9Efx47ZbAS4/Xc0KRedrqbzVIQvrlTvdejatzgK3Pb w==; X-IronPort-AV: E=McAfee;i="6200,9189,10252"; a="229748234" X-IronPort-AV: E=Sophos;i="5.88,354,1635231600"; d="scan'208";a="229748234" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2022 18:00:39 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,354,1635231600"; d="scan'208";a="678310019" Received: from fmsmsx605.amr.corp.intel.com ([10.18.126.85]) by fmsmga001.fm.intel.com with ESMTP; 08 Feb 2022 18:00:39 -0800 Received: from shsmsx606.ccr.corp.intel.com (10.109.6.216) by fmsmsx605.amr.corp.intel.com (10.18.126.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.20; Tue, 8 Feb 2022 18:00:39 -0800 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by SHSMSX606.ccr.corp.intel.com (10.109.6.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.20; Wed, 9 Feb 2022 10:00:37 +0800 Received: from shsmsx601.ccr.corp.intel.com ([10.109.6.141]) by SHSMSX601.ccr.corp.intel.com ([10.109.6.141]) with mapi id 15.01.2308.020; Wed, 9 Feb 2022 10:00:37 +0800 From: "Zhang, Qi Z" To: Kathleen Capella CC: "dev@dpdk.org" , "nd@arm.com" , "dharmik.thakkar@arm.com" , "honnappa.nagarahalli@arm.com" Subject: RE: [PATCH 0/2] Add logic to IAVF to count continuous DD bits for Arm Thread-Topic: [PATCH 0/2] Add logic to IAVF to count continuous DD bits for Arm Thread-Index: AQHYGicWko9rc60qm0Cbx1e9g0F2mayKfQWw Date: Wed, 9 Feb 2022 02:00:37 +0000 Message-ID: References: <20220205002630.31841-1-kathleen.capella@arm.com> In-Reply-To: <20220205002630.31841-1-kathleen.capella@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.6.200.16 dlp-product: dlpe-windows x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: Kathleen Capella > Sent: Saturday, February 5, 2022 8:26 AM > Cc: dev@dpdk.org; nd@arm.com; dharmik.thakkar@arm.com; > honnappa.nagarahalli@arm.com; Kathleen Capella > > Subject: [PATCH 0/2] Add logic to IAVF to count continuous DD bits for Ar= m >=20 > This patchset introduces a fix for Arm platforms to the IAVF driver that = was > added to the i40e driver in a previous patchset [1]. >=20 > The driver determines which descriptors in the HW ring reference packets > that are ready to be received by counting those descriptors whose DD bit = is > set to 1. On Arm, the reading of descriptors can be reordered. The CPU ma= y > be reading descriptors as the NIC is updating them. Tt is possbile that t= he DD > bit for a descriptor earlier in the queue is read as not set while the DD= bit for > a descriptor later in the queue is read as set. This patchset ensures onl= y > contiguous DD bits set to 1 are counted. >=20 > The first patch in this series adds this logic to the bulk Rx path. > The second patch adds this same logic to the function which reads flexibl= e Rx > descriptors. >=20 > No performance drop was observed when running l3fwd on N1SDP with a > single core. >=20 > [1] > https://patches.dpdk.org/project/dpdk/patch/20210706065404.25137-2- > joyce.kong@arm.com/ >=20 > Kathleen Capella (2): > net/iavf: count continuous DD bits for Arm > net/iavf: count continuous DD bits for Arm in flex Rx >=20 > drivers/net/iavf/iavf_rxtx.c | 52 ++++++++++++++++++++++++++++++------ > 1 file changed, 44 insertions(+), 8 deletions(-) >=20 > -- > 2.17.1 Reviewed-by: Qi Zhang Applied to dpdk-next-net-intel. Thanks Qi