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charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH] net/ice: fix queue bind MSI-X interrupt error X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 2/19/2020 10:17 AM, taox.zhu@intel.com wrote: > From: Zhu Tao > > To bind a queue to an MSI-X interrupt, need to set some register. > The register consists of many parts, each of which has several > bits; therefore, the shift operator '<<' was used; so the operator > '<' in the code should be '<<'. > > Old code adds 1 on even MSI-X interrupt vector index used by queue, > resulting in interrupt mapping error. > > Fixes: 65dfc889d8 ("net/ice: support Rx queue interruption") > Cc: stable@dpdk.org > > Signed-off-by: Zhu Tao > --- > drivers/net/ice/ice_ethdev.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c > index 8e9369e0a..85ef83e92 100644 > --- a/drivers/net/ice/ice_ethdev.c > +++ b/drivers/net/ice/ice_ethdev.c > @@ -2605,9 +2605,9 @@ __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect, > for (i = 0; i < nb_queue; i++) { > /*do actual bind*/ > val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) | > - (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M; > + (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M; > val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) | > - (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M; > + (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M; Hi Tao, Out of curiosity, what is the point of left shifting "0"?