From: Raslan Darawsheh <rasland@nvidia.com>
To: Gregory Etelson <getelson@nvidia.com>, dev@dpdk.org
Cc: mkashani@nvidia.com, Michael Baum <michaelba@nvidia.com>,
dsosnowski@nvidia.com,
Viacheslav Ovsiienko <viacheslavo@nvidia.com>,
Bing Zhao <bingz@nvidia.com>, Ori Kam <orika@nvidia.com>,
Suanming Mou <suanmingm@nvidia.com>,
Matan Azrad <matan@nvidia.com>
Subject: Re: [PATCH 1/3] net/mlx5: fix multi process Tx default rules
Date: Sun, 2 Nov 2025 09:32:24 +0200 [thread overview]
Message-ID: <f1218a2a-9f8b-43b2-96cd-94d87038c6ef@nvidia.com> (raw)
In-Reply-To: <20251029155711.169580-1-getelson@nvidia.com>
Hi,
On 29/10/2025 5:57 PM, Gregory Etelson wrote:
> From: Michael Baum <michaelba@nvidia.com>
>
> When representor matching is disabled, an egress default rule is
> inserted which matches all and copies REG_A to REG_C_1 (when dv_xmeta_en
> == 4) and jump to group 1. All user rules started from group 1.
>
> When 2 processes are working together, the first one creates this flow
> rule and the second one is failed with errno EEXIST. This renders all
> user egress rules in 2nd process to be invalid.
>
> This patch changes this default rule match on SQs.
>
> Fixes: 483181f7b6dd ("net/mlx5: support device control of representor matching")
> Cc: dsosnowski@nvidia.com
>
> Signed-off-by: Michael Baum <michaelba@nvidia.com>
> Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
>
Series applied to next-net-mlx,
Kindest regards
Raslan Darawsheh
prev parent reply other threads:[~2025-11-02 7:32 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-29 15:57 Gregory Etelson
2025-10-29 15:57 ` [PATCH 2/3] net/mlx5: fix control flow leakage for external SQ Gregory Etelson
2025-10-29 15:57 ` [PATCH 3/3] net/mlx5: support flow metadata exchange between E-Switch and VM Gregory Etelson
2025-11-02 7:32 ` Raslan Darawsheh [this message]
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