From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id A460DA04B6; Mon, 12 Oct 2020 21:47:37 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 319841D9B6; Mon, 12 Oct 2020 21:47:36 +0200 (CEST) Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by dpdk.org (Postfix) with ESMTP id 725771D9B5 for ; Mon, 12 Oct 2020 21:47:34 +0200 (CEST) Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 09CJXFGw049014; Mon, 12 Oct 2020 15:47:28 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=subject : to : cc : references : from : message-id : date : mime-version : in-reply-to : content-type : content-transfer-encoding; s=pp1; bh=fUsanimo2Muw1p2u1y8U+eMWiZxYmqvQUIRjrefhkr8=; b=WOA4GSh/iYSqmkR93qmXT84P7j7CadSvXdrTorqOaICJTvg6i5tVubOVsnkDon+aZZTs fLYQzuTOPxvw3VaKDYkhQwitT+Ak9nFHktSuaH0OWyGMgNpJ9fYt/1JHrszQ+IcFdjl+ vOkqMFJ1ajGwBGi4Alv5uF8jK0t+tx3THMqJYUgHzwDv16GkPEHBX8VlpdhwtoCNwwuH 1/Zsg9rKwjYIwC7MySp1jXXmk/+gXhBnmQbmgD5O9YUW2pX3E+SwDnapU6qZnAvy0Bo7 qs+1L4y8d9O8g9zwJnCdH0IO2ez9XhK+gmKZDb+5iumMX/6Dt86I+cfVj8W9dxmKNYaK xA== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 344w51gnd0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 12 Oct 2020 15:47:28 -0400 Received: from m0098410.ppops.net (m0098410.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 09CJXFHb048978; Mon, 12 Oct 2020 15:47:28 -0400 Received: from ppma03wdc.us.ibm.com (ba.79.3fa9.ip4.static.sl-reverse.com [169.63.121.186]) by mx0a-001b2d01.pphosted.com with ESMTP id 344w51gncn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 12 Oct 2020 15:47:28 -0400 Received: from pps.filterd (ppma03wdc.us.ibm.com [127.0.0.1]) by ppma03wdc.us.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 09CJkVRI030055; Mon, 12 Oct 2020 19:47:27 GMT Received: from b03cxnp08028.gho.boulder.ibm.com (b03cxnp08028.gho.boulder.ibm.com [9.17.130.20]) by ppma03wdc.us.ibm.com with ESMTP id 343y2st1jk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 12 Oct 2020 19:47:27 +0000 Received: from b03ledav003.gho.boulder.ibm.com (b03ledav003.gho.boulder.ibm.com [9.17.130.234]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 09CJlQA015794460 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 12 Oct 2020 19:47:26 GMT Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 04EA06A054; Mon, 12 Oct 2020 19:47:26 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5A1416A051; Mon, 12 Oct 2020 19:47:25 +0000 (GMT) Received: from Davids-MBP.randomparity.org (unknown [9.211.73.22]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Mon, 12 Oct 2020 19:47:25 +0000 (GMT) To: Anatoly Burakov , dev@dpdk.org Cc: Liang Ma , Jan Viktorin , Ruifeng Wang , Bruce Richardson , Konstantin Ananyev , david.hunt@intel.com, jerinjacobk@gmail.com, thomas@monjalon.net, timothy.mcdaniel@intel.com, gage.eads@intel.com, chris.macnamara@intel.com References: <532f45c5d79b4c30a919553d322bb66e91534466.1602258833.git.anatoly.burakov@intel.com> From: David Christensen Message-ID: Date: Mon, 12 Oct 2020 12:47:24 -0700 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:68.0) Gecko/20100101 Thunderbird/68.12.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-10-12_17:2020-10-12, 2020-10-12 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1011 lowpriorityscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 mlxscore=0 phishscore=0 bulkscore=0 adultscore=0 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2010120145 Subject: Re: [dpdk-dev] [PATCH v5 02/10] eal: add power management intrinsics X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 10/9/20 9:02 AM, Anatoly Burakov wrote: > From: Liang Ma > > Add two new power management intrinsics, and provide an implementation > in eal/x86 based on UMONITOR/UMWAIT instructions. The instructions > are implemented as raw byte opcodes because there is not yet widespread > compiler support for these instructions. > > The power management instructions provide an architecture-specific > function to either wait until a specified TSC timestamp is reached, or > optionally wait until either a TSC timestamp is reached or a memory > location is written to. The monitor function also provides an optional > comparison, to avoid sleeping when the expected write has already > happened, and no more writes are expected. > > For more details, please refer to Intel(R) 64 and IA-32 Architectures > Software Developer's Manual, Volume 2. > > Signed-off-by: Liang Ma > Signed-off-by: Anatoly Burakov > --- > > Notes: > v5: > - Removed return values > - Simplified intrinsics and hardcoded C0.2 state > - Added other arch stubs > ... snip ... > +++ b/lib/librte_eal/ppc/include/rte_power_intrinsics.h > @@ -0,0 +1,62 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2020 Intel Corporation > + */ > + > +#ifndef _RTE_POWER_INTRINSIC_PPC_H_ > +#define _RTE_POWER_INTRINSIC_PPC_H_ > + > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +#include > +#include > + > +#include "generic/rte_power_intrinsics.h" > + > +/** > + * This function is not supported on PPC64. > + * > + * @param p > + * Address to monitor for changes. Must be aligned on an 64-byte boundary. > + * @param expected_value > + * Before attempting the monitoring, the `p` address may be read and compared > + * against this value. If `value_mask` is zero, this step will be skipped. > + * @param value_mask > + * The 64-bit mask to use to extract current value from `p`. > + * @param tsc_timestamp > + * Maximum TSC timestamp to wait for. > + * > + * @return > + * - 0 on success > + */ > +static inline void rte_power_monitor(const volatile void *p, > + const uint64_t expected_value, const uint64_t value_mask, > + const uint64_t tsc_timestamp) > +{ > + RTE_SET_USED(p); > + RTE_SET_USED(expected_value); > + RTE_SET_USED(value_mask); > + RTE_SET_USED(tsc_timestamp); > +} > + > +/** > + * This function is not supported on PPC64. > + * > + * @param tsc_timestamp > + * Maximum TSC timestamp to wait for. > + * > + * @return > + * - 1 if wakeup was due to TSC timeout expiration. > + * - 0 if wakeup was due to other reasons. > + */ > +static inline void rte_power_pause(const uint64_t tsc_timestamp) > +{ > + RTE_SET_USED(tsc_timestamp); > +} > + > +#ifdef __cplusplus > +} > +#endif > + > +#endif /* _RTE_POWER_INTRINSIC_PPC_H_ */ I didn't find an equivalent instruction in the current 3.1 ISA, so not supported is correct for POWER. Acked-by: David Christensen