From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7F64CA0A02; Tue, 23 Mar 2021 14:52:06 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0AA204069E; Tue, 23 Mar 2021 14:52:06 +0100 (CET) Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) by mails.dpdk.org (Postfix) with ESMTP id E35A340689 for ; Tue, 23 Mar 2021 14:52:04 +0100 (CET) Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4F4Xmp5z5hz19H5c; Tue, 23 Mar 2021 21:50:02 +0800 (CST) Received: from [10.78.49.194] (10.78.49.194) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.498.0; Tue, 23 Mar 2021 21:51:56 +0800 To: Ruifeng Wang , "thomas@monjalon.net" , "ferruh.yigit@intel.com" CC: "dev@dpdk.org" , "linuxarm@openeuler.org" , nd References: <1612356396-21309-1-git-send-email-oulijun@huawei.com> <1615340142-19115-1-git-send-email-oulijun@huawei.com> <1615340142-19115-2-git-send-email-oulijun@huawei.com> From: oulijun Message-ID: Date: Tue, 23 Mar 2021 21:51:56 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.1.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="gbk"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.78.49.194] X-CFilter-Loop: Reflected Subject: Re: [dpdk-dev] [PATCH V2 1/4] config/arm: add Hisilicon kunpeng920 implementer X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" ÔÚ 2021/3/23 16:07, Ruifeng Wang дµÀ: >> -----Original Message----- >> From: dev On Behalf Of Lijun Ou >> Sent: Wednesday, March 10, 2021 9:36 AM >> To: thomas@monjalon.net; ferruh.yigit@intel.com >> Cc: dev@dpdk.org; linuxarm@openeuler.org >> Subject: [dpdk-dev] [PATCH V2 1/4] config/arm: add Hisilicon kunpeng920 >> implementer >> >> Here addes Kunpeng920 config back which was deleted. >> >> Fixes: 91c730fd4e09 ("config/arm: remove unused or superfluous variables") >> >> Signed-off-by: Chengchang Tang >> Signed-off-by: Lijun Ou >> --- >> V1->V2: >> - rewrite patch title. >> - split the patch into two. >> --- >> config/arm/meson.build | 20 ++++++++++++++++++++ >> 1 file changed, 20 insertions(+) >> >> diff --git a/config/arm/meson.build b/config/arm/meson.build index >> 00bc461..3826900 100644 >> --- a/config/arm/meson.build >> +++ b/config/arm/meson.build >> @@ -133,6 +133,25 @@ implementer_cavium = { >> } >> } >> >> +implementer_hisilicon = { >> + 'description': 'Hisilicon', >> + 'flags': [ >> + ['RTE_USE_C11_MEM_MODEL', true], >> + ['RTE_CACHE_LINE_SIZE', 128], > > Just want to double check. > One Kunpeng920 box I can access have cache line size 64B. > I have a question, which level does RTE_CACHE_LINE_SIZE refer to? For kunpeng920, L1/L2 cache size is 64B£¬L3 is 128B > Thanks. >> + ['RTE_MAX_NUMA_NODES', 4] >> + ], >> + 'part_number_config': { >> + '0xd01': { >> + 'machine_args': ['-march=armv8.2-a+crypto', >> + '-mtune=tsv110'], >> + 'flag': [['RTE_MACHINE', '"kunpeng920"'], >> + ['RTE_MAX_LCORE', 128], >> + ['RTE_ARM_FEATURE_ATOMICS', true] >> + ] >> + } >> + } >> +} >> + >> implementer_ampere = { >> 'description': 'Ampere Computing', >> 'flags': [ >> @@ -190,6 +209,7 @@ implementers = { >> 'generic': implementer_generic, >> '0x41': implementer_arm, >> '0x43': implementer_cavium, >> + '0x48': implementer_hisilicon, >> '0x50': implementer_ampere, >> '0x51': implementer_qualcomm, >> '0x56': implementer_marvell, >> -- >> 2.7.4 > > . >