From: Xiaoyu Min <jackmin@mellanox.com>
To: orika@mellanox.com, Matan Azrad <matan@mellanox.com>,
Shahaf Shuler <shahafs@mellanox.com>,
Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Cc: dev@dpdk.org
Subject: [dpdk-dev] [PATCH] net/mlx5: allow pattern start from IP
Date: Tue, 5 Nov 2019 10:03:09 +0200 [thread overview]
Message-ID: <f81bc331a495cd17f3e572d75231b0230ec830b6.1572940653.git.jackmin@mellanox.com> (raw)
Some applications, i.e. OVS, have rule like:
[1] pattern ipv4 / end actions ...
which intends to match ipv4 only on non-vlan ethernet and MLX5 NIC
supports this.
So PMD should accept this.
Fixes: 906a2efae8da ("net/mlx5: validate flow rule item order")
Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
drivers/net/mlx5/mlx5_flow.c | 28 ++++++++++------------------
1 file changed, 10 insertions(+), 18 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index b4b08f4c6c..24ea4a72b5 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -1276,11 +1276,17 @@ mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
return rte_flow_error_set(error, ENOTSUP,
RTE_FLOW_ERROR_TYPE_ITEM, item,
"multiple L2 layers not supported");
- if (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_L3))
+ if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_L3)) ||
+ (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_L3)))
return rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_ITEM, item,
- "inner L2 layer should not "
- "follow inner L3 layers");
+ "L2 layer should not follow "
+ "L3 layers");
+ if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_VLAN)) ||
+ (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_VLAN)))
+ return rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ITEM, item,
+ "L2 layer should not follow VLAN");
if (!mask)
mask = &rte_flow_item_eth_mask;
ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
@@ -1327,8 +1333,6 @@ mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
MLX5_FLOW_LAYER_OUTER_VLAN;
- const uint64_t l2m = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
- MLX5_FLOW_LAYER_OUTER_L2;
if (item_flags & vlanm)
return rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_ITEM, item,
@@ -1336,11 +1340,7 @@ mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
else if ((item_flags & l34m) != 0)
return rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_ITEM, item,
- "L2 layer cannot follow L3/L4 layer");
- else if ((item_flags & l2m) == 0)
- return rte_flow_error_set(error, EINVAL,
- RTE_FLOW_ERROR_TYPE_ITEM, item,
- "no L2 layer before VLAN");
+ "VLAN cannot follow L3/L4 layer");
if (!mask)
mask = &rte_flow_item_vlan_mask;
ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
@@ -1453,10 +1453,6 @@ mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
return rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_ITEM, item,
"L3 cannot follow an NVGRE layer.");
- else if (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L2))
- return rte_flow_error_set(error, EINVAL,
- RTE_FLOW_ERROR_TYPE_ITEM, item,
- "no L2 layer before IPV4");
if (!mask)
mask = &rte_flow_item_ipv4_mask;
else if (mask->hdr.next_proto_id != 0 &&
@@ -1548,10 +1544,6 @@ mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
return rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_ITEM, item,
"L3 cannot follow an NVGRE layer.");
- else if (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L2))
- return rte_flow_error_set(error, EINVAL,
- RTE_FLOW_ERROR_TYPE_ITEM, item,
- "no L2 layer before IPV6");
if (!mask)
mask = &rte_flow_item_ipv6_mask;
ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
--
2.24.0.rc0.3.g12a4aeaad8
next reply other threads:[~2019-11-05 8:09 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-05 8:03 Xiaoyu Min [this message]
2019-11-06 11:26 ` Ori Kam
2019-11-06 12:11 ` Slava Ovsiienko
2019-11-07 14:00 ` Raslan Darawsheh
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