From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3F32542651; Wed, 27 Sep 2023 10:28:30 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2A065402EB; Wed, 27 Sep 2023 10:28:30 +0200 (CEST) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mails.dpdk.org (Postfix) with ESMTP id 55BB2402CA for ; Wed, 27 Sep 2023 10:28:27 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1695803306; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oREwf0fSWCeRukcPqw+Jr9zlhNUL/WvQuon+EToi8kg=; b=Z6+iwrJz7oNM4C/lpbWKphwxtehlglc/Mn1VZhEYRIwOsuvMPtiE0B9vw/OOytYV0TsNRv BtGv7kpueJb3dYLDJNmzu5xojPIjdFk3+tQRQgwTxAtO/Ad2kGjidFQISsDyi3sJOanGCT PVh3eEWRLjXd1p4RQBHvn9fw+A7q1vs= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-617-obxIsOwbOuuh8cefwv_cTg-1; Wed, 27 Sep 2023 04:28:22 -0400 X-MC-Unique: obxIsOwbOuuh8cefwv_cTg-1 Received: from smtp.corp.redhat.com (int-mx09.intmail.prod.int.rdu2.redhat.com [10.11.54.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 4B7778039D4; Wed, 27 Sep 2023 08:28:22 +0000 (UTC) Received: from [10.39.208.19] (unknown [10.39.208.19]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 2C572492B16; Wed, 27 Sep 2023 08:28:21 +0000 (UTC) Message-ID: Date: Wed, 27 Sep 2023 10:28:19 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 To: Nicolas Chautru , dev@dpdk.org Cc: hemant.agrawal@nxp.com, david.marchand@redhat.com, hernan.vargas@intel.com References: <20230921204349.3285318-1-nicolas.chautru@intel.com> <20230921204349.3285318-5-nicolas.chautru@intel.com> From: Maxime Coquelin Subject: Re: [PATCH v2 4/7] baseband/acc: allocate FCW memory separately In-Reply-To: <20230921204349.3285318-5-nicolas.chautru@intel.com> X-Scanned-By: MIMEDefang 3.1 on 10.11.54.9 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On 9/21/23 22:43, Nicolas Chautru wrote: > This allows more flexibility to the FCW size for the > unified driver. No actual functional change. > > Signed-off-by: Nicolas Chautru > --- > drivers/baseband/acc/acc_common.h | 4 +++- > drivers/baseband/acc/rte_vrb_pmd.c | 25 ++++++++++++++++++++++++- > 2 files changed, 27 insertions(+), 2 deletions(-) > > diff --git a/drivers/baseband/acc/acc_common.h b/drivers/baseband/acc/acc_common.h > index df18506e75..b5ee113faf 100644 > --- a/drivers/baseband/acc/acc_common.h > +++ b/drivers/baseband/acc/acc_common.h > @@ -101,6 +101,7 @@ > #define ACC_NUM_QGRPS_PER_WORD 8 > #define ACC_MAX_NUM_QGRPS 32 > #define ACC_RING_SIZE_GRANULARITY 64 > +#define ACC_MAX_FCW_SIZE 128 > > /* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */ > #define ACC_N_ZC_1 66 /* N = 66 Zc for BG 1 */ > @@ -582,13 +583,14 @@ struct __rte_cache_aligned acc_queue { > uint32_t aq_enqueued; /* Count how many "batches" have been enqueued */ > uint32_t aq_dequeued; /* Count how many "batches" have been dequeued */ > uint32_t irq_enable; /* Enable ops dequeue interrupts if set to 1 */ > - struct rte_mempool *fcw_mempool; /* FCW mempool */ > enum rte_bbdev_op_type op_type; /* Type of this Queue: TE or TD */ > /* Internal Buffers for loopback input */ > uint8_t *lb_in; > uint8_t *lb_out; > + uint8_t *fcw_ring; > rte_iova_t lb_in_addr_iova; > rte_iova_t lb_out_addr_iova; > + rte_iova_t fcw_ring_addr_iova; > int8_t *derm_buffer; /* interim buffer for de-rm in SDK */ > struct acc_device *d; > }; > diff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c > index 6898a0f802..f460e9ea2a 100644 > --- a/drivers/baseband/acc/rte_vrb_pmd.c > +++ b/drivers/baseband/acc/rte_vrb_pmd.c > @@ -883,6 +883,25 @@ vrb_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, > goto free_companion_ring_addr; > } > > + q->fcw_ring = rte_zmalloc_socket(dev->device->driver->name, > + ACC_MAX_FCW_SIZE * d->sw_ring_max_depth, > + RTE_CACHE_LINE_SIZE, conf->socket); > + if (q->fcw_ring == NULL) { > + rte_bbdev_log(ERR, "Failed to allocate fcw_ring memory"); > + ret = -ENOMEM; > + goto free_companion_ring_addr; > + } > + q->fcw_ring_addr_iova = rte_malloc_virt2iova(q->fcw_ring); I see this is not done for other rte_malloc_virt2iova(), but this API may returns an error (RTE_BAD_IOVA), so it should be checked. > + > + /* For FFT we need to store the FCW separately */ > + if (conf->op_type == RTE_BBDEV_OP_FFT) { > + for (desc_idx = 0; desc_idx < d->sw_ring_max_depth; desc_idx++) { > + desc = q->ring_addr + desc_idx; > + desc->req.data_ptrs[0].address = q->fcw_ring_addr_iova + > + desc_idx * ACC_MAX_FCW_SIZE; > + } > + } > + > q->qgrp_id = (q_idx >> VRB1_GRP_ID_SHIFT) & 0xF; > q->vf_id = (q_idx >> VRB1_VF_ID_SHIFT) & 0x3F; > q->aq_id = q_idx & 0xF; > @@ -994,6 +1013,7 @@ vrb_queue_release(struct rte_bbdev *dev, uint16_t q_id) > if (q != NULL) { > /* Mark the Queue as un-assigned. */ > d->q_assigned_bit_map[q->qgrp_id] &= (~0ULL - (1 << (uint64_t) q->aq_id)); > + rte_free(q->fcw_ring); > rte_free(q->companion_ring_addr); > rte_free(q->lb_in); > rte_free(q->lb_out); > @@ -3224,7 +3244,10 @@ vrb_enqueue_fft_one_op(struct acc_queue *q, struct rte_bbdev_fft_op *op, > output = op->fft.base_output.data; > in_offset = op->fft.base_input.offset; > out_offset = op->fft.base_output.offset; > - fcw = &desc->req.fcw_fft; > + > + fcw = (struct acc_fcw_fft *) (q->fcw_ring + > + ((q->sw_ring_head + total_enqueued_cbs) & q->sw_ring_wrap_mask) > + * ACC_MAX_FCW_SIZE); > > vrb1_fcw_fft_fill(op, fcw); > vrb1_dma_desc_fft_fill(op, &desc->req, input, output, &in_offset, &out_offset); With above suggested check added, the patch looks good to me. Thanks, Maxime