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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:xir-pvapexch01.xlnx.xilinx.com; PTR:unknown-80-198.xilinx.com; CAT:NONE; SFS:(13230022)(4636009)(376002)(346002)(136003)(39860400002)(396003)(451199015)(46966006)(40470700004)(35950700001)(498600001)(5660300002)(26005)(41300700001)(40480700001)(53546011)(4744005)(44832011)(40460700003)(45080400002)(36756003)(2906002)(110136005)(54906003)(316002)(86362001)(31696002)(82310400005)(8936002)(70206006)(70586007)(7636003)(9786002)(356005)(8676002)(31686004)(83380400001)(47076005)(4326008)(2616005)(82740400003)(336012)(50156003)(43740500002); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.onmicrosoft.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Sep 2022 17:55:52.5328 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aeaef254-5658-4225-b35a-08da9bfa8687 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.80.198]; Helo=[xir-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0060.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB6875 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On 9/8/2022 10:58 PM, longli@linuxonhyperv.com wrote: > From: Long Li > > MANA hardware has iommu built-in, that provides hardware safe access to > user memory through memory registration. Since memory registration is an > expensive operation, this patch implements a two level memory registration > cache mechanisum for each queue and for each port. s/mechanisum/mechanism/ > > Signed-off-by: Long Li <...>