From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id CCA93A034C; Tue, 18 Aug 2020 12:52:28 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 964601C020; Tue, 18 Aug 2020 12:52:27 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id DDC202B91 for ; Tue, 18 Aug 2020 12:52:25 +0200 (CEST) IronPort-SDR: IG0xWiX7e5kTgAvSosaMHHCCKkoJDbM561NRRdpaw5MjkXJDY/DumAyV0qh1xPL2vlFhlZAdt0 zFG/UEhFPXlw== X-IronPort-AV: E=McAfee;i="6000,8403,9716"; a="142706100" X-IronPort-AV: E=Sophos;i="5.76,327,1592895600"; d="scan'208";a="142706100" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2020 03:52:24 -0700 IronPort-SDR: 48/68g7v5ZBfdUqgKfbrGuOZhsjMrTja09QzK+80q1k0VwlWyI5yZT6gzLaYiDuQLaQuWtVcpd PLsAmbYr/MTw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,327,1592895600"; d="scan'208";a="328935040" Received: from jguo15x-mobl.ccr.corp.intel.com (HELO [10.67.68.178]) ([10.67.68.178]) by fmsmga002.fm.intel.com with ESMTP; 18 Aug 2020 03:52:16 -0700 To: kirankumark@marvell.com, Wenzhuo Lu , Beilei Xing , Bernard Iremonger , Thomas Monjalon , Ferruh Yigit , Andrew Rybchenko Cc: dev@dpdk.org, jerinj@marvell.com, orika@mellanox.com, xuanziyang2@huawei.com, cloud.wangxiaoyun@huawei.com, zhouguoyang@huawei.com, rosen.xu@intel.com, rmody@marvell.com, shshaikh@marvell.com, ndabilpuram@marvell.com, qiming.yang@intel.com, qi.z.zhang@intel.com, keith.wiles@intel.com, hemant.agrawal@nxp.com, sachin.saxena@nxp.com, wei.zhao1@intel.com, johndale@cisco.com, hyonkim@cisco.com, chas3@att.com, matan@mellanox.com, shahafs@mellanox.com, viacheslavo@mellanox.com, rahul.lakkireddy@chelsio.com, grive@u256.net, lironh@marvell.com, jingjing.wu@intel.com, xavier.huwei@huawei.com, humin29@huawei.com, yisen.zhuang@huawei.com, ajit.khaparde@broadcom.com, somnath.kotur@broadcom.com, jasvinder.singh@intel.com, cristian.dumitrescu@intel.com References: <20200818072143.2189928-1-kirankumark@marvell.com> <20200818103145.2192371-1-kirankumark@marvell.com> From: Jeff Guo Message-ID: Date: Tue, 18 Aug 2020 18:52:15 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: <20200818103145.2192371-1-kirankumark@marvell.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US Subject: Re: [dpdk-dev] [PATCH v4 1/2] ethdev: add level support for RSS offload types X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" hi, kiran On 8/18/2020 6:31 PM, kirankumark@marvell.com wrote: > From: Kiran Kumar K > > This patch reserves 2 bits as input selection to select Inner and > outer layers for RSS computation. It is combined with existing > ETH_RSS_* to choose Inner or outer layers for L2, L3 and L4. > This functionality already exists in rte_flow through level parameter in > RSS action configuration rte_flow_action_rss. > > Signed-off-by: Kiran Kumar K > --- > app/test-pmd/parameters.c | 6 ++++++ > lib/librte_ethdev/rte_ethdev.h | 27 +++++++++++++++++++++++++++ > 2 files changed, 33 insertions(+) > > diff --git a/app/test-pmd/parameters.c b/app/test-pmd/parameters.c > index 7cb0e3d6e..5f669ff24 100644 > --- a/app/test-pmd/parameters.c > +++ b/app/test-pmd/parameters.c > @@ -632,6 +632,8 @@ launch_args_parse(int argc, char** argv) > { "forward-mode", 1, 0, 0 }, > { "rss-ip", 0, 0, 0 }, > { "rss-udp", 0, 0, 0 }, > + { "rss-outer", 0, 0, 0 }, > + { "rss-inner-outer", 0, 0, 0 }, > { "rxq", 1, 0, 0 }, > { "txq", 1, 0, 0 }, > { "rxd", 1, 0, 0 }, > @@ -1051,6 +1053,10 @@ launch_args_parse(int argc, char** argv) > rss_hf = ETH_RSS_IP; > if (!strcmp(lgopts[opt_idx].name, "rss-udp")) > rss_hf = ETH_RSS_UDP; > + if (!strcmp(lgopts[opt_idx].name, "rss-outer")) > + rss_hf |= ETH_RSS_LEVEL_OUTER; > + if (!strcmp(lgopts[opt_idx].name, "rss-inner-outer")) > + rss_hf |= ETH_RSS_LEVEL_INNER_OUTER; > if (!strcmp(lgopts[opt_idx].name, "rxq")) { > n = atoi(optarg); > if (n >= 0 && check_nb_rxq((queueid_t)n) == 0) > diff --git a/lib/librte_ethdev/rte_ethdev.h b/lib/librte_ethdev/rte_ethdev.h > index d29930fd8..28184cc85 100644 > --- a/lib/librte_ethdev/rte_ethdev.h > +++ b/lib/librte_ethdev/rte_ethdev.h > @@ -552,6 +552,33 @@ struct rte_eth_rss_conf { > #define RTE_ETH_RSS_L3_PRE64 (1ULL << 53) > #define RTE_ETH_RSS_L3_PRE96 (1ULL << 52) > > +/* > + * We use the following macros to combine with the above layers to choose > + * inner and outer layers or both for RSS computation. > + * Note: Default is 0: inner layers, 1: outer layers, 2: both > + * bit 50 and 51 are reserved for this. Why not define outermost layer to 0, and the inner layer is on the same direction to increase? Do you think it would be good to default set outer hash? > + */ > + > +/** > + * Level 0, It basically stands for the innermost encapsulation level RSS > + * can be performed on according to PMD and device capabilities. > + */ > +#define ETH_RSS_LEVEL_INNER (0ULL << 50) > +/** > + * Level 1, It basically stands for the outermost encapsulation level RSS > + * can be performed on according to PMD and device capabilities. > + */ > +#define ETH_RSS_LEVEL_OUTER (1ULL << 50) > +/** > + * Level 2, It basically stands for the both inner and outermost > + * encapsulation level RSS can be performed on according to PMD and > + * device capabilities. > + */ > +#define ETH_RSS_LEVEL_INNER_OUTER (2ULL << 50) > +#define ETH_RSS_LEVEL_MASK (3ULL << 50) > + > +#define ETH_RSS_LEVEL(rss_hf) ((rss_hf & ETH_RSS_LEVEL_MASK) >> 50) > + > /** > * For input set change of hash filter, if SRC_ONLY and DST_ONLY of > * the same level are used simultaneously, it is the same case as