From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3BA80A0A03; Tue, 19 Jan 2021 08:43:17 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B9BB8140D06; Tue, 19 Jan 2021 08:43:16 +0100 (CET) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 0BF5B140CF4; Tue, 19 Jan 2021 08:43:14 +0100 (CET) IronPort-SDR: Jt2q5QLzE4lwDZ5RdDJb+bs6f3V8zDEl67c7Pd3s8mA3dfBUswI88ybZ+H8Ma2pg3DeWqdPz+5 BYg0ZQMT6O0A== X-IronPort-AV: E=McAfee;i="6000,8403,9868"; a="179040114" X-IronPort-AV: E=Sophos;i="5.79,358,1602572400"; d="scan'208";a="179040114" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jan 2021 23:43:07 -0800 IronPort-SDR: +Rqo1a62+0eMb3glJiN/FTTBH9q7m39NLySf/xwdZQlE2RlFRARNBitBhwVdtNHp/lt5iUcBY5 iJV5+ohuobQQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,358,1602572400"; d="scan'208";a="353719468" Received: from fmsmsx602.amr.corp.intel.com ([10.18.126.82]) by orsmga006.jf.intel.com with ESMTP; 18 Jan 2021 23:43:07 -0800 Received: from shsmsx604.ccr.corp.intel.com (10.109.6.214) by fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Mon, 18 Jan 2021 23:43:05 -0800 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by SHSMSX604.ccr.corp.intel.com (10.109.6.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Tue, 19 Jan 2021 15:43:03 +0800 Received: from shsmsx601.ccr.corp.intel.com ([10.109.6.141]) by SHSMSX601.ccr.corp.intel.com ([10.109.6.141]) with mapi id 15.01.1713.004; Tue, 19 Jan 2021 15:43:03 +0800 From: "Guo, Jia" To: "Wu, Wenjun1" , "dev@dpdk.org" , "Zhang, Qi Z" , "Zhang, Yuying" CC: "stable@dpdk.org" Thread-Topic: [PATCH v1] net/e1000: fix the invalid flow control mode setting Thread-Index: AQHW7jJ5P0TXsD4xuUCUbFmpxXgB0aoujYow Date: Tue, 19 Jan 2021 07:43:03 +0000 Message-ID: References: <20210119065847.66043-1-wenjun1.wu@intel.com> In-Reply-To: <20210119065847.66043-1-wenjun1.wu@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v1] net/e1000: fix the invalid flow control mode setting X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi, Wenjun > -----Original Message----- > From: Wu, Wenjun1 > Sent: Tuesday, January 19, 2021 2:59 PM > To: dev@dpdk.org; Guo, Jia ; Zhang, Qi Z > ; Zhang, Yuying > Cc: Wu, Wenjun1 ; stable@dpdk.org > Subject: [PATCH v1] net/e1000: fix the invalid flow control mode setting >=20 > E1000_CTRL register should be updated according to fc_conf->mode's value. >=20 > Fixes: af75078fece3 ("first public release") > Cc: stable@dpdk.org >=20 > Signed-off-by: Wenjun Wu > --- > drivers/net/e1000/igb_ethdev.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) >=20 > diff --git a/drivers/net/e1000/igb_ethdev.c > b/drivers/net/e1000/igb_ethdev.c index 647aa8d99..390737393 100644 > --- a/drivers/net/e1000/igb_ethdev.c > +++ b/drivers/net/e1000/igb_ethdev.c > @@ -3064,6 +3064,7 @@ eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, > struct rte_eth_fc_conf *fc_conf) > uint32_t rx_buf_size; > uint32_t max_high_water; > uint32_t rctl; > + uint32_t ctrl; >=20 > hw =3D E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); > if (fc_conf->autoneg !=3D hw->mac.autoneg) @@ -3101,6 +3102,15 > @@ eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf > *fc_conf) > rctl &=3D ~E1000_RCTL_PMCF; >=20 > E1000_WRITE_REG(hw, E1000_RCTL, rctl); > + Some document for ctrl, like rctl setting, would be appreciate. > + ctrl =3D E1000_READ_REG(hw, E1000_CTRL); > + ctrl &=3D ~(E1000_CTRL_RFCE|E1000_CTRL_TFCE); > + if (fc_conf->mode =3D=3D RTE_FC_RX_PAUSE || fc_conf->mode > =3D=3D RTE_FC_FULL) > + ctrl |=3D E1000_CTRL_RFCE; > + if (fc_conf->mode =3D=3D RTE_FC_TX_PAUSE || fc_conf->mode > =3D=3D RTE_FC_FULL) > + ctrl |=3D E1000_CTRL_TFCE; What about the case if fc_conf->mode =3D=3D RTE_FC_NONE? Use a switch would= be help for that? > + E1000_WRITE_REG(hw, E1000_CTRL, ctrl); > + > E1000_WRITE_FLUSH(hw); >=20 > return 0; > -- > 2.25.1